[llvm-commits] [llvm] r150774 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-ret.ll

[Chad Rosier]

Author: mcrosier
Date: Thu Feb 16 19:21:28 2012
New Revision: 150774

URL: http://llvm.org/viewvc/llvm-project?rev=150774&view=rev
Log:
[fast-isel] Add support for returning non-legal types with no sign- or zero-
entend flag.


Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=150774&r1=150773&r2=150774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Feb 16 19:21:28 2012
@@ -2037,14 +2037,14 @@
       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
         return false;
 
-      if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
-        return false;
-
       assert(DestVT == MVT::i32 && "ARM should always ext to i32");
 
-      bool isZExt = Outs[0].Flags.isZExt();
-      SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, isZExt);
-      if (SrcReg == 0) return false;
+      // Perform extension if flagged as either zext or sext.  Otherwise, do
+      // nothing.
+      if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
+        SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
+        if (SrcReg == 0) return false;
+      }
     }
 
     // Make the copy.

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll?rev=150774&r1=150773&r2=150774&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll Thu Feb 16 19:21:28 2012
@@ -46,3 +46,12 @@
 ; CHECK: bx lr
   ret i16 %a
 }
+
+define i16 @ret6(i16 %a) nounwind uwtable ssp {
+entry:
+; CHECK: ret6
+; CHECK-NOT: uxth
+; CHECK-NOT: sxth
+; CHECK: bx lr
+  ret i16 %a
+}