[llvm-commits] [llvm] r150655 - in /llvm/trunk/lib: CodeGen/MachineCSE.cpp Target/ARM/ARMBaseRegisterInfo.cpp

[Lang Hames]

Author: lhames
Date: Wed Feb 15 20:32:10 2012
New Revision: 150655

URL: http://llvm.org/viewvc/llvm-project?rev=150655&view=rev
Log:
Oop - r150653 + r150654 broke one of my test cases. Backing out for now...

Modified:
    llvm/trunk/lib/CodeGen/MachineCSE.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=150655&r1=150654&r2=150655&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Wed Feb 15 20:32:10 2012
@@ -63,8 +63,6 @@
     virtual void releaseMemory() {
       ScopeMap.clear();
       Exps.clear();
-      AllocatableRegs.clear();
-      ReservedRegs.clear();
     }
 
   private:
@@ -78,8 +76,6 @@
     ScopedHTType VNT;
     SmallVector<MachineInstr*, 64> Exps;
     unsigned CurrVN;
-    BitVector AllocatableRegs;
-    BitVector ReservedRegs;
 
     bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
     bool isPhysDefTriviallyDead(unsigned Reg,
@@ -240,9 +236,9 @@
       return false;
 
     for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
-      if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i]))
-        // Avoid extending live range of physical registers if they are
-        //allocatable or reserved.
+      if (TRI->isInAllocatableClass(PhysDefs[i]))
+        // Avoid extending live range of physical registers unless
+        // they are unallocatable.
         return false;
     }
     CrossMBB = true;
@@ -592,7 +588,5 @@
   MRI = &MF.getRegInfo();
   AA = &getAnalysis<AliasAnalysis>();
   DT = &getAnalysis<MachineDominatorTree>();
-  AllocatableRegs = TRI->getAllocatableSet(MF);
-  ReservedRegs = TRI->getReservedRegs(MF);
   return PerformCSE(DT->getRootNode());
 }

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=150655&r1=150654&r2=150655&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Feb 15 20:32:10 2012
@@ -79,6 +79,7 @@
   BitVector Reserved(getNumRegs());
   Reserved.set(ARM::SP);
   Reserved.set(ARM::PC);
+  Reserved.set(ARM::FPSCR);
   if (TFI->hasFP(MF))
     Reserved.set(FramePtr);
   if (hasBasePointer(MF))