[llvm-commits] Fix LLVM to emit 16-bit CMN when targeting ARM Thumb2 ISA

[Sebastian Pop]

Hi,

I would like to ping this patch: could one of the ARM maintainers please review
the attached patch?

Thanks,
Sebastian

On Tue, Jan 24, 2012 at 6:08 PM, Zino Benaissa <zinob at codeaurora.org> wrote:
> Description:
>
> As per request from Jacob, I isolated the fix to CMN instruction so that
> LLVM emits 16-bits CMN instruction. This fix allows mapping t2CMNzrr to
> tCMNz.
>
>
>
> Modified:
>
>    test/CodeGen/Thumb2/thumb2-cmn.ll
>
>    lib/Target/ARM/Thumb2SizeReduction.cpp
>
>
>
> Modified:
>
> Index: test/CodeGen/Thumb2/thumb2-cmn.ll
>
> ===================================================================
>
> --- test/CodeGen/Thumb2/thumb2-cmn.ll          (revision 148675)
>
> +++ test/CodeGen/Thumb2/thumb2-cmn.ll       (working copy)
>
> @@ -9,7 +9,7 @@
>
>      ret i1 %tmp
>
> }
>
> ; CHECK: f1:
>
> -; CHECK:             cmn.w  r0, r1
>
> +; CHECK:            cmn       r0, r1
>
>
>
>  define i1 @f2(i32 %a, i32 %b) {
>
>      %nb = sub i32 0, %b
>
> @@ -17,7 +17,7 @@
>
>      ret i1 %tmp
>
> }
>
> ; CHECK: f2:
>
> -; CHECK:             cmn.w  r0, r1
>
> +; CHECK:            cmn       r0, r1
>
>
>
>  define i1 @f3(i32 %a, i32 %b) {
>
>      %nb = sub i32 0, %b
>
> @@ -25,7 +25,7 @@
>
>      ret i1 %tmp
>
> }
>
> ; CHECK: f3:
>
> -; CHECK:             cmn.w  r0, r1
>
> +; CHECK:            cmn       r0, r1
>
>
>
>  define i1 @f4(i32 %a, i32 %b) {
>
>      %nb = sub i32 0, %b
>
> @@ -33,7 +33,7 @@
>
>      ret i1 %tmp
>
> }
>
> ; CHECK: f4:
>
> -; CHECK:             cmn.w  r0, r1
>
> +; CHECK:            cmn       r0, r1
>
>
>
>  define i1 @f5(i32 %a, i32 %b) {
>
>      %tmp = shl i32 %b, 5
>
>
>
> Index: lib/Target/ARM/Thumb2SizeReduction.cpp
>
> ===================================================================
>
> --- lib/Target/ARM/Thumb2SizeReduction.cpp  (revision 148675)
>
> +++ lib/Target/ARM/Thumb2SizeReduction.cpp               (working copy)
>
> @@ -67,6 +67,7 @@
>
>      { ARM::t2BICrr, 0,            ARM::tBIC,     0,   0,    0,   1,  0,0,
> 1,0 },
>
>      //FIXME: Disable CMN, as CCodes are backwards from compare expectations
>
>      //{ ARM::t2CMNrr, ARM::tCMN,  0,             0,   0,    1,   0,  2,0,
> 0,0 },
>
> +    { ARM::t2CMNzrr, ARM::tCMNz,  0,             0,   0,    1,   0,  2,0,
> 0,0 },
>
>      { ARM::t2CMPri, ARM::tCMPi8,  0,             8,   0,    1,   0,  2,0,
> 0,0 },
>
>      { ARM::t2CMPrr, ARM::tCMPhir, 0,             0,   0,    0,   0,  2,0,
> 0,1 },
>
>      { ARM::t2EORrr, 0,            ARM::tEOR,     0,   0,    0,   1,  0,0,
> 1,0 },
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>

--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
-------------- next part --------------
Index: test/CodeGen/Thumb2/thumb2-cmn.ll
===================================================================
--- test/CodeGen/Thumb2/thumb2-cmn.ll          (revision 148675)
+++ test/CodeGen/Thumb2/thumb2-cmn.ll       (working copy)
@@ -9,7 +9,7 @@
     ret i1 %tmp
}
; CHECK: f1:
-; CHECK:             cmn.w  r0, r1
+; CHECK:             cmn  r0, r1
 
 define i1 @f2(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
@@ -17,7 +17,7 @@
     ret i1 %tmp
}
; CHECK: f2:
-; CHECK:             cmn.w  r0, r1
+; CHECK:             cmn  r0, r1
 
 define i1 @f3(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
@@ -25,7 +25,7 @@
     ret i1 %tmp
}
; CHECK: f3:
-; CHECK:             cmn.w  r0, r1
+; CHECK:             cmn  r0, r1
 
 define i1 @f4(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
@@ -33,7 +33,7 @@
     ret i1 %tmp
}
; CHECK: f4:
-; CHECK:             cmn.w  r0, r1
+; CHECK:             cmn  r0, r1
 
 define i1 @f5(i32 %a, i32 %b) {
     %tmp = shl i32 %b, 5
 
Index: lib/Target/ARM/Thumb2SizeReduction.cpp
===================================================================
--- lib/Target/ARM/Thumb2SizeReduction.cpp  (revision 148675)
+++ lib/Target/ARM/Thumb2SizeReduction.cpp               (working copy)
@@ -67,6 +67,7 @@
     { ARM::t2BICrr, 0,            ARM::tBIC,     0,   0,    0,   1,  0,0, 1,0 },
     //FIXME: Disable CMN, as CCodes are backwards from compare expectations
     //{ ARM::t2CMNrr, ARM::tCMN,  0,             0,   0,    1,   0,  2,0, 0,0 },
+    { ARM::t2CMNzrr, ARM::tCMNz,  0,             0,   0,    1,   0,  2,0, 0,0 },
     { ARM::t2CMPri, ARM::tCMPi8,  0,             8,   0,    1,   0,  2,0, 0,0 },
     { ARM::t2CMPrr, ARM::tCMPhir, 0,             0,   0,    0,   0,  2,0, 0,1 },
     { ARM::t2EORrr, 0,            ARM::tEOR,     0,   0,    0,   1,  0,0, 1,0 },