[llvm-commits] [llvm] r150633 - in /llvm/trunk: include/llvm/CodeGen/DFAPacketizer.h lib/CodeGen/DFAPacketizer.cpp

[Andrew Trick]

Author: atrick
Date: Wed Feb 15 17:34:15 2012
New Revision: 150633

URL: http://llvm.org/viewvc/llvm-project?rev=150633&view=rev
Log:
Fix library visibility problems with VLIWPacketizer.

The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface.

Modified:
    llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h
    llvm/trunk/lib/CodeGen/DFAPacketizer.cpp

Modified: llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h?rev=150633&r1=150632&r2=150633&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h Wed Feb 15 17:34:15 2012
@@ -36,7 +36,7 @@
 class MachineLoopInfo;
 class MachineDominatorTree;
 class InstrItineraryData;
-class ScheduleDAGInstrs;
+class VLIWPacketizerImpl;
 class SUnit;
 
 class DFAPacketizer {
@@ -91,8 +91,8 @@
   const MachineFunction &MF;
   const TargetInstrInfo *TII;
 
-  // The VLIW Scheduler.
-  ScheduleDAGInstrs *VLIWScheduler;
+  // Encapsulate data types not exposed to the target interface.
+  VLIWPacketizerImpl *Impl;
 
 protected:
   // Vector of instructions assigned to the current packet.

Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=150633&r1=150632&r2=150633&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Wed Feb 15 17:34:15 2012
@@ -103,15 +103,29 @@
 namespace {
 // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
 // Schedule method to build the dependence graph.
+//
+// ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so cannot be exposed to the
+// VLIWPacketizerImpl interface, even as an undefined pointer.
 class DefaultVLIWScheduler : public ScheduleDAGInstrs {
 public:
   DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
-                   MachineDominatorTree &MDT, bool IsPostRA);
+                       MachineDominatorTree &MDT, bool IsPostRA);
   // Schedule - Actual scheduling work.
   void Schedule();
 };
 }
 
+namespace llvm {
+// Wrapper for holding library-local data types.
+class VLIWPacketizerImpl {
+public:
+  DefaultVLIWScheduler DAGBuilder;
+  VLIWPacketizerImpl(MachineFunction &MF, MachineLoopInfo &MLI,
+                     MachineDominatorTree &MDT, bool IsPostRA)
+    : DAGBuilder(MF, MLI, MDT, IsPostRA) {}
+};
+}
+
 DefaultVLIWScheduler::DefaultVLIWScheduler(
   MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
   bool IsPostRA) :
@@ -129,12 +143,12 @@
   bool IsPostRA) : TM(MF.getTarget()), MF(MF)  {
   TII = TM.getInstrInfo();
   ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
-  VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
+  Impl = new VLIWPacketizerImpl(MF, MLI, MDT, IsPostRA);
 }
 
 // VLIWPacketizerList Dtor
 VLIWPacketizerList::~VLIWPacketizerList() {
-  delete VLIWScheduler;
+  delete Impl;
   delete ResourceTracker;
 }
 
@@ -181,11 +195,10 @@
 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
                                       MachineBasicBlock::iterator BeginItr,
                                       MachineBasicBlock::iterator EndItr) {
-  assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
-  VLIWScheduler->Run(MBB, BeginItr, EndItr, MBB->size());
+  Impl->DAGBuilder.Run(MBB, BeginItr, EndItr, MBB->size());
 
   // Remember scheduling units.
-  SUnits = VLIWScheduler->SUnits;
+  SUnits = Impl->DAGBuilder.SUnits;
 
   // Generate MI -> SU map.
   std::map <MachineInstr*, SUnit*> MIToSUnit;