[llvm-commits] [llvm] r150360 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_zext.ll
Craig Topper
craig.topper at gmail.com
Sun Feb 12 20:30:38 PST 2012
Author: ctopper
Date: Sun Feb 12 22:30:38 2012
New Revision: 150360
URL: http://llvm.org/viewvc/llvm-project?rev=150360&view=rev
Log:
Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/vec_zext.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=150360&r1=150359&r2=150360&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Feb 12 22:30:38 2012
@@ -6186,8 +6186,11 @@
return false;
// Skip one more bit_convert if necessary
- if (V.getOpcode() == ISD::BITCAST)
+ if (V.getOpcode() == ISD::BITCAST) {
+ if (!V.hasOneUse())
+ return false;
V = V.getOperand(0);
+ }
if (!ISD::isNormalLoad(V.getNode()))
return false;
Modified: llvm/trunk/test/CodeGen/X86/vec_zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_zext.ll?rev=150360&r1=150359&r2=150360&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_zext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_zext.ll Sun Feb 12 22:30:38 2012
@@ -1,26 +1,6 @@
; RUN: llc < %s -march=x86-64
; PR 9267
-define<4 x i32> @func_16_32() {
- %F = load <4 x i16>* undef
- %G = zext <4 x i16> %F to <4 x i32>
- %H = load <4 x i16>* undef
- %Y = zext <4 x i16> %H to <4 x i32>
- %T = add <4 x i32> %Y, %G
- store <4 x i32>%T , <4 x i32>* undef
- ret <4 x i32> %T
-}
-
-define<4 x i64> @func_16_64() {
- %F = load <4 x i16>* undef
- %G = zext <4 x i16> %F to <4 x i64>
- %H = load <4 x i16>* undef
- %Y = zext <4 x i16> %H to <4 x i64>
- %T = xor <4 x i64> %Y, %G
- store <4 x i64>%T , <4 x i64>* undef
- ret <4 x i64> %T
-}
-
define<4 x i64> @func_32_64() {
%F = load <4 x i32>* undef
%G = zext <4 x i32> %F to <4 x i64>
@@ -29,41 +9,3 @@
%T = or <4 x i64> %Y, %G
ret <4 x i64> %T
}
-
-define<4 x i16> @func_8_16() {
- %F = load <4 x i8>* undef
- %G = zext <4 x i8> %F to <4 x i16>
- %H = load <4 x i8>* undef
- %Y = zext <4 x i8> %H to <4 x i16>
- %T = add <4 x i16> %Y, %G
- ret <4 x i16> %T
-}
-
-define<4 x i32> @func_8_32() {
- %F = load <4 x i8>* undef
- %G = zext <4 x i8> %F to <4 x i32>
- %H = load <4 x i8>* undef
- %Y = zext <4 x i8> %H to <4 x i32>
- %T = sub <4 x i32> %Y, %G
- ret <4 x i32> %T
-}
-
-define<4 x i64> @func_8_64() {
- %F = load <4 x i8>* undef
- %G = zext <4 x i8> %F to <4 x i64>
- %H = load <4 x i8>* undef
- %Y = zext <4 x i8> %H to <4 x i64>
- %T = add <4 x i64> %Y, %G
- ret <4 x i64> %T
-}
-
-define<4 x i32> @const_16_32() {
- %G = zext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i32>
- ret <4 x i32> %G
-}
-
-define<4 x i64> @const_16_64() {
- %G = zext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i64>
- ret <4 x i64> %G
-}
-
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