[llvm-commits] [llvm] r150047 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-binary.ll

[Chad Rosier]

Author: mcrosier
Date: Tue Feb  7 20:45:44 2012
New Revision: 150047

URL: http://llvm.org/viewvc/llvm-project?rev=150047&view=rev
Log:
[fast-isel] Add support for SUBs with non-legal types.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=150047&r1=150046&r2=150047&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Feb  7 20:45:44 2012
@@ -1749,6 +1749,9 @@
     case ISD::OR:
       Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
       break;
+    case ISD::SUB:
+      Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
+      break;
   }
 
   unsigned SrcReg1 = getRegForValue(I->getOperand(0));
@@ -2509,6 +2512,8 @@
       return SelectBinaryIntOp(I, ISD::ADD);
     case Instruction::Or:
       return SelectBinaryIntOp(I, ISD::OR);
+    case Instruction::Sub:
+      return SelectBinaryIntOp(I, ISD::SUB);
     case Instruction::FAdd:
       return SelectBinaryFPOp(I, ISD::FADD);
     case Instruction::FSub:

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll?rev=150047&r1=150046&r2=150047&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll Tue Feb  7 20:45:44 2012
@@ -76,3 +76,41 @@
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
+
+; Test sub with non-legal types
+
+define void @sub_i1(i1 %a, i1 %b) nounwind ssp {
+entry:
+; ARM: sub_i1
+; THUMB: sub_i1
+  %a.addr = alloca i1, align 4
+  %0 = sub i1 %a, %b
+; ARM: sub r0, r0, r1
+; THUMB: subs r0, r0, r1
+  store i1 %0, i1* %a.addr, align 4
+  ret void
+}
+
+define void @sub_i8(i8 %a, i8 %b) nounwind ssp {
+entry:
+; ARM: sub_i8
+; THUMB: sub_i8
+  %a.addr = alloca i8, align 4
+  %0 = sub i8 %a, %b
+; ARM: sub r0, r0, r1
+; THUMB: subs r0, r0, r1
+  store i8 %0, i8* %a.addr, align 4
+  ret void
+}
+
+define void @sub_i16(i16 %a, i16 %b) nounwind ssp {
+entry:
+; ARM: sub_i16
+; THUMB: sub_i16
+  %a.addr = alloca i16, align 4
+  %0 = sub i16 %a, %b
+; ARM: sub r0, r0, r1
+; THUMB: subs r0, r0, r1
+  store i16 %0, i16* %a.addr, align 4
+  ret void
+}