[llvm-commits] [llvm] r150045 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-binary.ll

[Chad Rosier]

Author: mcrosier
Date: Tue Feb  7 20:29:21 2012
New Revision: 150045

URL: http://llvm.org/viewvc/llvm-project?rev=150045&view=rev
Log:
[fast-isel] Add support for ORs with non-legal types.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=150045&r1=150044&r2=150045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Feb  7 20:29:21 2012
@@ -1733,7 +1733,6 @@
 }
 
 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
-  assert (ISDOpcode == ISD::ADD && "Expected an add.");
   EVT DestVT  = TLI.getValueType(I->getType(), true);
 
   // We can get here in the case when we have a binary operation on a non-legal
@@ -1741,6 +1740,17 @@
   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
     return false;
   
+  unsigned Opc;
+  switch (ISDOpcode) {
+    default: return false;
+    case ISD::ADD:
+      Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
+      break;
+    case ISD::OR:
+      Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
+      break;
+  }
+
   unsigned SrcReg1 = getRegForValue(I->getOperand(0));
   if (SrcReg1 == 0) return false;
 
@@ -1749,7 +1759,6 @@
   unsigned SrcReg2 = getRegForValue(I->getOperand(1));
   if (SrcReg2 == 0) return false;
 
-  unsigned Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
   unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                           TII.get(Opc), ResultReg)
@@ -2498,6 +2507,8 @@
       return SelectFPToI(I, /*isSigned*/ false);
     case Instruction::Add:
       return SelectBinaryIntOp(I, ISD::ADD);
+    case Instruction::Or:
+      return SelectBinaryIntOp(I, ISD::OR);
     case Instruction::FAdd:
       return SelectBinaryFPOp(I, ISD::FADD);
     case Instruction::FSub:

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll?rev=150045&r1=150044&r2=150045&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-binary.ll Tue Feb  7 20:29:21 2012
@@ -38,3 +38,39 @@
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
+
+define void @or_i1(i1 %a, i1 %b) nounwind ssp {
+entry:
+; ARM: or_i1
+; THUMB: or_i1
+  %a.addr = alloca i1, align 4
+  %0 = or i1 %a, %b
+; ARM: orr r0, r0, r1
+; THUMB: orrs r0, r1
+  store i1 %0, i1* %a.addr, align 4
+  ret void
+}
+
+define void @or_i8(i8 %a, i8 %b) nounwind ssp {
+entry:
+; ARM: or_i8
+; THUMB: or_i8
+  %a.addr = alloca i8, align 4
+  %0 = or i8 %a, %b
+; ARM: orr r0, r0, r1
+; THUMB: orrs r0, r1
+  store i8 %0, i8* %a.addr, align 4
+  ret void
+}
+
+define void @or_i16(i16 %a, i16 %b) nounwind ssp {
+entry:
+; ARM: or_i16
+; THUMB: or_i16
+  %a.addr = alloca i16, align 4
+  %0 = or i16 %a, %b
+; ARM: orr r0, r0, r1
+; THUMB: orrs r0, r1
+  store i16 %0, i16* %a.addr, align 4
+  ret void
+}