[llvm-commits] [PATCH] Teach the MC about UNPREDICTABLE

James Molloy james.molloy at arm.com
Mon Feb 6 02:42:57 PST 2012



ARM has the concept of an "unpredictable" instruction - one which is valid
(and will be executed) but whose results are not defined. An example of an
unpredictable instruction is a load with address increment and writeback
where the writeback register is the same as the load destination.


The MC disassembler has the concept of a "soft failure" which maps well to
unpredictability (coincidentally because it was added for that purpose).
However this soft failure can currently only be triggered by manual C++ code
such as that in ARMDisassembler.cpp - it cannot be triggered from
tablegen-generated code.


The attached patch adds this functionality. It adds the ability for the
FixedLenDecoderEmitter to take into account a bitfield in a tablegen record
called "SoftFail" that mirrors the "Inst" field.


If a bitpattern BP matches the Inst field of an instruction record but
differs from Inst in any bits which are set to '1' in the SoftFail field,
then that instruction is matched by the disassembler but the status SoftFail
is returned instead of Success.


For example, this is a modified Thumb BX instruction with unpredictability
modelled as per the ARMARM:


def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,

            T1Special<{1,1,0,?}> {

    // A6.2.3 & A8.6.25

    bits<4> Rm;

    let Inst{6-3} = Rm;

    let Inst{2-0} = 0b000;

    // Any of the bottom 3 bits set is unpredictable.

    let SoftFail{2-0} = 0b111;



And this is the generated disassembler code (new code bolded):


if ((Bits & ARM::ModeThumb)) {

  if (insn & 0x7)

    S = MCDisassembler::SoftFail;


  tmp = fieldFromInstruction16(insn, 3, 4);

  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return

    return S; // tBXT



This results in the MC now correctly identifying such an instruction:


$ echo '0x01 0x47' | ./bin/llvm-mc -triple thumbv7 -disassemble

<stdin>:1:1: warning: potentially undefined instruction encoding

0x01 0x47


                bx           r0


The patch works by removing any bits that could SoftFail from the set of
possible disassembly island values, and emitting an extra test if required
in the generated disassembler. If no SoftFail bits are set, no extra code
will be emitted.


In the ARM tablegen files, this patch aliases SoftFail to "Unpredictable" so
it is more recognisable what it is doing in the ARM world.


Please review! It wires the new functionality up to "tBX" as a proof of
concept and testing codepath, and adds a regression test.




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