[llvm-commits] [llvm] r149823 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Nadav Rotem nadav.rotem at intel.com
Sun Feb 5 03:39:23 PST 2012


Author: nadav
Date: Sun Feb  5 05:39:23 2012
New Revision: 149823

URL: http://llvm.org/viewvc/llvm-project?rev=149823&view=rev
Log:
Add additional documentation to the extract-and-trunc dagcombine optimization.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=149823&r1=149822&r2=149823&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Feb  5 05:39:23 2012
@@ -4985,9 +4985,14 @@
       return N0.getOperand(0);
   }
 
-  // Fold Extract-and-trunc into a narrow extract:
-  //    trunc(extract(x)) -> extract(bitcast(x))
-  // We only run this optimization after type legalization (which often
+  // Fold extract-and-trunc into a narrow extract. For example:
+  //   i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
+  //   i32 y = TRUNCATE(i64 x)
+  //        -- becomes --
+  //   v16i8 b = BITCAST (v2i64 val)
+  //   i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
+  //
+  // Note: We only run this optimization after type legalization (which often
   // creates this pattern) and before operation legalization after which
   // we need to be more careful about the vector instructions that we generate.
   if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&





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