[llvm-commits] [PATCH 01/13] Add For Loop Structures

[David A. Greene]

"Rotem, Nadav" <nadav.rotem at intel.com> writes:

> David, 
>
> Maybe I missed this in previous emails, but I am not sure what is the motivation for the zip operator. 

So someone can iterate over multiple values.  For example, one might
want to (probably not, but bear with me for the example) do this for x86:

list<ValueTypes> Vector128Types = [v4f32, v2f64, v4i32, v2i64];
list<ValueTypes> Vector256Types = [v8f32, v4f64, v8i32, v4i64];

foreach RegNum = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  foreach {string Prefix, list<ValueType> Types} TypeInfo = 
          !zip(["X", "Y"], [Vector128Types, Vector256Types]) {
    def TypeInfo.Prefix#MM#RegNum : Reg<...> {
       list<ValueType> RepresentableTypes = TypeInfo.Types;
       ...
    }
  }
}

Again, take this as an example of how it would be used, not necessarily
a suggestion to define x86 vector registers this way.  The point is that
one can't use nested foreach to so something like this.

                           -Dave