[llvm-commits] Tuning LLVM Greedy Register Allocator to optimize for code size when targeting ARM Thumb 2 instruction set

[Jakob Stoklund Olesen]

On Jan 24, 2012, at 10:25 AM, Chad Rosier wrote:

> On Jan 23, 2012, at 9:46 PM, Zino Benaissa wrote:
> 
>> From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] If you don't mind, I would like you to run a couple of experiments to better understand why this change improves some benchmarks.
>>  
>> Ø    Sure,  please let me know what you find.
> 
> Just to be clear, I believe Jakob was suggesting *you* run the experiments.

Oh, sorry if that wasn't clear.

>> First of all, is the regHasSizeImpact() hook necessary? Do you get significantly different results if you pretend this function always returns 2?
>>  
>> Ø    For my experiments,  precision is quite important to maximize code size gains.

The thing is, the function is using information that isn't yet available at RA time. For example, you look at <kill> flags, but they will be changed by the post-RA scheduler moving instructions around. You look at load/store offsets, but they are not filled in until PEI runs. You can't really know which instructions can be converted to 2-address form until after RA etc.

So basically, regHasSizeImpact() returns a guess, it has to.

Another guess that is much faster to compute is '2'.

I want to know which guess is better, because if there is only a small difference, we can leave out a lot of code and save compile time.

/jakob

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