[llvm-commits] [llvm] r148485 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/X86/intel-syntax-encoding.s

[Chris Lattner]

On Jan 19, 2012, at 9:53 AM, Devang Patel wrote:

> Author: dpatel
> Date: Thu Jan 19 11:53:25 2012
> New Revision: 148485
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=148485&view=rev
> Log:
> Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.

Hi Devang,

Why don't the normal patterns for XOR16ri8 and friends work?  This seems like it will affect a *large* number of instructions.

-Chris

> 
> Added:
>    llvm/trunk/test/MC/X86/intel-syntax-encoding.s
> Modified:
>    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
> 
> Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=148485&r1=148484&r2=148485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jan 19 11:53:25 2012
> @@ -1217,6 +1217,120 @@
>     Inst = TmpInst;
>     return true;
>   }
> +  case X86::XOR16i16: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::XOR16ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
> +  case X86::XOR32i32: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::XOR32ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
> +  case X86::XOR64i32: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::XOR64ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
> +  case X86::OR16i16: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::OR16ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
> +  case X86::OR32i32: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::OR32ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
> +  case X86::OR64i32: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::OR64ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
> +  case X86::CMP16i16: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::CMP16ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
> +  case X86::CMP32i32: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::CMP32ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
> +  case X86::CMP64i32: {
> +    if (!Inst.getOperand(0).isImm() ||
> +        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
> +      return false;
> +
> +    MCInst TmpInst;
> +    TmpInst.setOpcode(X86::CMP64ri8);
> +    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
> +    TmpInst.addOperand(Inst.getOperand(0));
> +    Inst = TmpInst;
> +    return true;
> +  }
>   }
>   return false;
> }
> 
> Added: llvm/trunk/test/MC/X86/intel-syntax-encoding.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax-encoding.s?rev=148485&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/X86/intel-syntax-encoding.s (added)
> +++ llvm/trunk/test/MC/X86/intel-syntax-encoding.s Thu Jan 19 11:53:25 2012
> @@ -0,0 +1,22 @@
> +// RUN: llvm-mc -x86-asm-syntax=intel -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
> +
> +// CHECK: encoding: [0x66,0x83,0xf0,0x0c]
> +	xor	ax, 12
> +// CHECK: encoding: [0x83,0xf0,0x0c]
> +	xor	eax, 12
> +// CHECK: encoding: [0x48,0x83,0xf0,0x0c]
> +	xor	rax, 12
> +
> +// CHECK: encoding: [0x66,0x83,0xc8,0x0c]
> +	or	ax, 12
> +// CHECK: encoding: [0x83,0xc8,0x0c]
> +	or	eax, 12
> +// CHECK: encoding: [0x48,0x83,0xc8,0x0c]
> +	or	rax, 12
> +
> +// CHECK: encoding: [0x66,0x83,0xf8,0x0c]
> +	cmp	ax, 12
> +// CHECK: encoding: [0x83,0xf8,0x0c]
> +	cmp	eax, 12
> +// CHECK: encoding: [0x48,0x83,0xf8,0x0c]
> +	cmp	rax, 12
> 
> 
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