[llvm-commits] [llvm] r148473 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp test/CodeGen/ARM/ehabi-unwind.ll

[Evgeniy Stepanov]

Author: eugenis
Date: Thu Jan 19 06:53:06 2012
New Revision: 148473

URL: http://llvm.org/viewvc/llvm-project?rev=148473&view=rev
Log:
Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.


Added:
    llvm/trunk/test/CodeGen/ARM/ehabi-unwind.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=148473&r1=148472&r2=148473&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jan 19 06:53:06 2012
@@ -1107,6 +1107,7 @@
       break;
     case ARM::STR_PRE_IMM:
     case ARM::STR_PRE_REG:
+    case ARM::t2STR_PRE:
       assert(MI->getOperand(2).getReg() == ARM::SP &&
              "Only stack pointer as a source reg is supported");
       RegList.push_back(SrcReg);
@@ -1122,12 +1123,14 @@
         MI->dump();
         assert(0 && "Unsupported opcode for unwinding information");
       case ARM::MOVr:
+      case ARM::tMOVr:
         Offset = 0;
         break;
       case ARM::ADDri:
         Offset = -MI->getOperand(2).getImm();
         break;
       case ARM::SUBri:
+      case ARM::t2SUBri:
         Offset = MI->getOperand(2).getImm();
         break;
       case ARM::tSUBspi:

Added: llvm/trunk/test/CodeGen/ARM/ehabi-unwind.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ehabi-unwind.ll?rev=148473&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ehabi-unwind.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/ehabi-unwind.ll Thu Jan 19 06:53:06 2012
@@ -0,0 +1,15 @@
+; Test that the EHABI unwind instruction generator does not encounter any
+; unfamiliar instructions.
+; RUN: llc < %s -mtriple=thumbv7 -arm-enable-ehabi -disable-fp-elim
+; RUN: llc < %s -mtriple=thumbv7 -arm-enable-ehabi
+
+define void @_Z1fv() nounwind {
+entry:
+  ret void
+}
+
+define void @_Z1gv() nounwind {
+entry:
+  call void @_Z1fv()
+  ret void
+}