[llvm-commits] [llvm] r148422 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

[Jim Grosbach]

Author: grosbach
Date: Wed Jan 18 15:54:09 2012
New Revision: 148422

URL: http://llvm.org/viewvc/llvm-project?rev=148422&view=rev
Log:
Rename pattern for clarity.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=148422&r1=148421&r2=148422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Jan 18 15:54:09 2012
@@ -672,10 +672,9 @@
 }
 
 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
-// For disassembly use only.
-def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
-                       "ldr", "\t$Rt, $addr",
-                       [/* disassembly only */]>,
+// For assembly/disassembly use only.
+def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
+                       "ldr", "\t$Rt, $addr", []>,
                  T1Encoding<{0,1,0,0,1,?}> {
   // A6.2 & A8.6.59
   bits<3> Rt;