[llvm-commits] [llvm] r148272 - in /llvm/trunk: include/llvm/ADT/BitVector.h unittests/ADT/BitVectorTest.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Mon Jan 16 23:35:38 PST 2012
On Jan 16, 2012, at 8:58 PM, Chandler Carruth wrote:
> On Mon, Jan 16, 2012 at 8:32 PM, Chris Lattner <clattner at apple.com> wrote:
> On Jan 16, 2012, at 5:24 PM, Jakob Stoklund Olesen wrote:
> > Author: stoklund
> > Date: Mon Jan 16 19:24:32 2012
> > New Revision: 148272
> > URL: http://llvm.org/viewvc/llvm-project?rev=148272&view=rev
> > Log:
> > Add portable bit mask operations to BitVector.
> > BitVector uses the native word size for its internal representation.
> > That doesn't work well for literal bit masks in source code.
> > This patch adds BitVector operations to efficiently apply literal bit
> > masks specified as arrays of uint32_t. Since each array entry always
> > holds exactly 32 bits, these portable bit masks can be source code
> > literals, probably produced by TableGen.
> Out of curiosity, why not arrays of uint64_t? It will be faster on 64-bit platforms, and shouldn't really be a penalty on 32-bit either.
It's a speed / size tradeoff. The typical use case is bit vectors of physical registers, which means a bit vector with 160 entries on x86. Using uint64_t would mean a 20% space overhead compared to uint32_t.
The inner loop of applyMask was supposed to unroll and optimize to 64-bit operations with an unaligned load as the only regression. LLVM's optimizers disagree, though, and we get:
LBB14_2: ## %for.body
## =>This Inner Loop Header: Depth=1
movl (%rsi), %ebx
orq (%r8,%r9,8), %rbx
movl 4(%rsi), %eax
shlq $32, %rax
orq %rbx, %rax
movq %rax, (%r8,%r9,8)
addq $8, %rsi
addl $-2, %edi
cmpl $1, %edi
I couldn't trick LLVM into combining the two 32-bit loads, presumably because of missing alignment.
On 32-bit architectures, the applyMask code is much smaller.
> I wondered the same thing. I also wondered about an array of indices rather than an array of bits.. Specifically, an array of indices would seem easier to read, and if they're all likely to be literals, I would expect the optimizer to make them all equivalent...
That would only work when the literals are directly visible to the optimizer. In this case, pointers will be passed through virtual functions. I am not concerned with readability since the bit masks will be produced by TableGen.
BitVector already supports this use case well with the existing methods. See for example the targets' getReservedRegs() implementations.
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