[llvm-commits] [llvm] r148289 - in /llvm/trunk: include/llvm/Target/TargetOptions.h lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/RegAllocGreedy.cpp lib/Target/TargetMachine.cpp

[Andrew Trick]

Author: atrick
Date: Tue Jan 17 00:54:59 2012
New Revision: 148289

URL: http://llvm.org/viewvc/llvm-project?rev=148289&view=rev
Log:
Moving options declarations around.

More short term hackery until we have a way to configure passes that work on LiveIntervals.

Modified:
    llvm/trunk/include/llvm/Target/TargetOptions.h
    llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
    llvm/trunk/lib/Target/TargetMachine.cpp

Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=148289&r1=148288&r2=148289&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOptions.h Tue Jan 17 00:54:59 2012
@@ -34,10 +34,6 @@
   /// wth earlier copy coalescing.
   extern bool StrongPHIElim;
 
-  /// EnableMachineSched - temporary flag to enable the machine scheduling pass
-  /// until we complete the register allocation pass configuration cleanup.
-  extern bool EnableMachineSched;
-
   class TargetOptions {
   public:
     TargetOptions()

Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=148289&r1=148288&r2=148289&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Jan 17 00:54:59 2012
@@ -149,8 +149,6 @@
   if (StrongPHIElim)
     AU.addRequiredID(StrongPHIEliminationID);
   AU.addRequiredTransitiveID(RegisterCoalescerPassID);
-  if (EnableMachineSched)
-    AU.addRequiredID(MachineSchedulerPassID);
   AU.addRequired<CalculateSpillWeights>();
   AU.addRequired<LiveStacks>();
   AU.addPreserved<LiveStacks>();

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=148289&r1=148288&r2=148289&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Jan 17 00:54:59 2012
@@ -51,6 +51,13 @@
 STATISTIC(NumLocalSplits,  "Number of split local live ranges");
 STATISTIC(NumEvicted,      "Number of interferences evicted");
 
+/// EnableMachineSched - temporary flag to enable the machine scheduling pass
+/// until we complete the register allocation pass configuration cleanup.
+static cl::opt<bool>
+EnableMachineSched("enable-misched",
+                   cl::desc("Enable the machine instruction scheduling pass."),
+                   cl::init(false), cl::Hidden);
+
 static cl::opt<SplitEditor::ComplementSpillMode>
 SplitSpillMode("split-spill-mode", cl::Hidden,
   cl::desc("Spill mode for splitting live ranges"),

Modified: llvm/trunk/lib/Target/TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=148289&r1=148288&r2=148289&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/TargetMachine.cpp Tue Jan 17 00:54:59 2012
@@ -37,14 +37,6 @@
   cl::desc("Emit functions into separate sections"),
   cl::init(false));
 
-/// EnableMachineSched - temporary flag to enable the machine scheduling pass
-/// until we complete the register allocation pass configuration cleanup.
-static cl::opt<bool, true>
-MachineSchedOpt("enable-misched",
-                cl::desc("Enable the machine instruction scheduling pass."),
-                cl::location(EnableMachineSched),
-                cl::init(false), cl::Hidden);
-
 //---------------------------------------------------------------------------
 // TargetMachine Class
 //