[llvm-commits] [llvm] r148105 - in /llvm/trunk: include/llvm/CodeGen/Passes.h include/llvm/InitializePasses.h include/llvm/Target/TargetOptions.h lib/CodeGen/CMakeLists.txt lib/CodeGen/CodeGen.cpp lib/CodeGen/MachineScheduler.cpp lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/RegAllocGreedy.cpp lib/Target/TargetMachine.cpp
Evan Cheng
evan.cheng at apple.com
Mon Jan 16 09:48:49 PST 2012
Hi Andy,
Can we avoid adding anything to TargetOptions.h? Noticed now there is a TargetOptions class that capture codegen options.
Does it make sense to add MISched to "basic" reg-allocator? If not, then you can move the command line option into RegAllocGreedy.cpp.
Evan
On Jan 12, 2012, at 10:30 PM, Andrew Trick wrote:
> Author: atrick
> Date: Fri Jan 13 00:30:30 2012
> New Revision: 148105
>
> URL: http://llvm.org/viewvc/llvm-project?rev=148105&view=rev
> Log:
> Added the MachineSchedulerPass skeleton.
>
> Added:
> llvm/trunk/lib/CodeGen/MachineScheduler.cpp
> Modified:
> llvm/trunk/include/llvm/CodeGen/Passes.h
> llvm/trunk/include/llvm/InitializePasses.h
> llvm/trunk/include/llvm/Target/TargetOptions.h
> llvm/trunk/lib/CodeGen/CMakeLists.txt
> llvm/trunk/lib/CodeGen/CodeGen.cpp
> llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
> llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
> llvm/trunk/lib/Target/TargetMachine.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=148105&r1=148104&r2=148105&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/Passes.h Fri Jan 13 00:30:30 2012
> @@ -84,6 +84,9 @@
> /// RegisteCoalescer pass - This pass merges live ranges to eliminate copies.
> extern char &RegisterCoalescerPassID;
>
> + /// MachineScheduler pass - This pass schedules machine instructions.
> + extern char &MachineSchedulerPassID;
> +
> /// SpillPlacement analysis. Suggest optimal placement of spill code between
> /// basic blocks.
> ///
>
> Modified: llvm/trunk/include/llvm/InitializePasses.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=148105&r1=148104&r2=148105&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/InitializePasses.h (original)
> +++ llvm/trunk/include/llvm/InitializePasses.h Fri Jan 13 00:30:30 2012
> @@ -156,6 +156,7 @@
> void initializeMachineLoopInfoPass(PassRegistry&);
> void initializeMachineLoopRangesPass(PassRegistry&);
> void initializeMachineModuleInfoPass(PassRegistry&);
> +void initializeMachineSchedulerPassPass(PassRegistry&);
> void initializeMachineSinkingPass(PassRegistry&);
> void initializeMachineVerifierPassPass(PassRegistry&);
> void initializeMemCpyOptPass(PassRegistry&);
>
> Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=148105&r1=148104&r2=148105&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetOptions.h Fri Jan 13 00:30:30 2012
> @@ -34,6 +34,10 @@
> /// wth earlier copy coalescing.
> extern bool StrongPHIElim;
>
> + /// EnableMachineSched - temporary flag to enable the machine scheduling pass
> + /// until we complete the register allocation pass configuration cleanup.
> + extern bool EnableMachineSched;
> +
> class TargetOptions {
> public:
> TargetOptions()
>
> Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=148105&r1=148104&r2=148105&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original)
> +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Fri Jan 13 00:30:30 2012
> @@ -57,6 +57,7 @@
> MachinePassRegistry.cpp
> MachineRegisterInfo.cpp
> MachineSSAUpdater.cpp
> + MachineScheduler.cpp
> MachineSink.cpp
> MachineVerifier.cpp
> OcamlGC.cpp
>
> Modified: llvm/trunk/lib/CodeGen/CodeGen.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CodeGen.cpp?rev=148105&r1=148104&r2=148105&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/CodeGen.cpp (original)
> +++ llvm/trunk/lib/CodeGen/CodeGen.cpp Fri Jan 13 00:30:30 2012
> @@ -43,6 +43,7 @@
> initializeProcessImplicitDefsPass(Registry);
> initializePEIPass(Registry);
> initializeRegisterCoalescerPass(Registry);
> + initializeMachineSchedulerPassPass(Registry);
> initializeRenderMachineFunctionPass(Registry);
> initializeSlotIndexesPass(Registry);
> initializeStackProtectorPass(Registry);
>
> Added: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=148105&view=auto
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (added)
> +++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Fri Jan 13 00:30:30 2012
> @@ -0,0 +1,233 @@
> +//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// MachineScheduler schedules machine instructions after phi elimination. It
> +// preserves LiveIntervals so it can be invoked before register allocation.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#define DEBUG_TYPE "misched"
> +
> +#include "ScheduleDAGInstrs.h"
> +#include "LiveDebugVariables.h"
> +#include "llvm/CodeGen/LiveIntervalAnalysis.h"
> +#include "llvm/CodeGen/MachinePassRegistry.h"
> +#include "llvm/CodeGen/Passes.h"
> +#include "llvm/Analysis/AliasAnalysis.h"
> +#include "llvm/Support/CommandLine.h"
> +#include "llvm/Support/Debug.h"
> +#include "llvm/Support/ErrorHandling.h"
> +#include "llvm/Support/raw_ostream.h"
> +#include "llvm/ADT/OwningPtr.h"
> +
> +using namespace llvm;
> +
> +namespace {
> +/// MachineSchedulerPass runs after coalescing and before register allocation.
> +class MachineSchedulerPass : public MachineFunctionPass {
> +public:
> + MachineFunction *MF;
> + const MachineLoopInfo *MLI;
> + const MachineDominatorTree *MDT;
> +
> + MachineSchedulerPass();
> +
> + virtual void getAnalysisUsage(AnalysisUsage &AU) const;
> +
> + virtual void releaseMemory() {}
> +
> + virtual bool runOnMachineFunction(MachineFunction&);
> +
> + virtual void print(raw_ostream &O, const Module* = 0) const;
> +
> + static char ID; // Class identification, replacement for typeinfo
> +};
> +} // namespace
> +
> +char MachineSchedulerPass::ID = 0;
> +
> +char &llvm::MachineSchedulerPassID = MachineSchedulerPass::ID;
> +
> +INITIALIZE_PASS_BEGIN(MachineSchedulerPass, "misched",
> + "Machine Instruction Scheduler", false, false)
> +INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
> +INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
> +INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
> +INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
> +INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
> +INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
> +INITIALIZE_PASS_END(MachineSchedulerPass, "misched",
> + "Machine Instruction Scheduler", false, false)
> +
> +MachineSchedulerPass::MachineSchedulerPass()
> +: MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
> + initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
> +}
> +
> +void MachineSchedulerPass::getAnalysisUsage(AnalysisUsage &AU) const {
> + AU.setPreservesCFG();
> + AU.addRequiredID(MachineDominatorsID);
> + AU.addRequired<MachineLoopInfo>();
> + AU.addRequired<AliasAnalysis>();
> + AU.addPreserved<AliasAnalysis>();
> + AU.addRequired<SlotIndexes>();
> + AU.addPreserved<SlotIndexes>();
> + AU.addRequired<LiveIntervals>();
> + AU.addPreserved<LiveIntervals>();
> + AU.addRequired<LiveDebugVariables>();
> + AU.addPreserved<LiveDebugVariables>();
> + if (StrongPHIElim) {
> + AU.addRequiredID(StrongPHIEliminationID);
> + AU.addPreservedID(StrongPHIEliminationID);
> + }
> + AU.addRequiredID(RegisterCoalescerPassID);
> + AU.addPreservedID(RegisterCoalescerPassID);
> + MachineFunctionPass::getAnalysisUsage(AU);
> +}
> +
> +namespace {
> +/// Currently force DAG building but don't reschedule anything. This is a
> +/// temporarily useful framework that provides a place to hook in experimental
> +/// code that requires a dependence graph prior to register allocation.
> +class MachineScheduler : public ScheduleDAGInstrs {
> +public:
> + MachineScheduler(MachineSchedulerPass *P)
> + : ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT)
> + {}
> +
> + /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
> + /// time to do some work.
> + virtual void Schedule();
> +};
> +} // namespace
> +
> +namespace {
> +/// MachineSchedRegistry provides a selection of available machine instruction
> +/// schedulers.
> +class MachineSchedRegistry : public MachinePassRegistryNode {
> +public:
> + typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedulerPass *);
> +
> + // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
> + typedef ScheduleDAGCtor FunctionPassCtor;
> +
> + static MachinePassRegistry Registry;
> +
> + MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
> + : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
> + Registry.Add(this);
> + }
> + ~MachineSchedRegistry() { Registry.Remove(this); }
> +
> + // Accessors.
> + //
> + MachineSchedRegistry *getNext() const {
> + return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
> + }
> + static MachineSchedRegistry *getList() {
> + return (MachineSchedRegistry *)Registry.getList();
> + }
> + static ScheduleDAGCtor getDefault() {
> + return (ScheduleDAGCtor)Registry.getDefault();
> + }
> + static void setDefault(ScheduleDAGCtor C) {
> + Registry.setDefault((MachinePassCtor)C);
> + }
> + static void setListener(MachinePassRegistryListener *L) {
> + Registry.setListener(L);
> + }
> +};
> +} // namespace
> +
> +MachinePassRegistry MachineSchedRegistry::Registry;
> +
> +static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P);
> +
> +/// MachineSchedOpt allows command line selection of the scheduler.
> +static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
> + RegisterPassParser<MachineSchedRegistry> >
> +MachineSchedOpt("misched",
> + cl::init(&createDefaultMachineSched), cl::Hidden,
> + cl::desc("Machine instruction scheduler to use"));
> +
> +static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P) {
> + return new MachineScheduler(P);
> +}
> +static MachineSchedRegistry
> +SchedDefaultRegistry("default", "Activate the scheduler pass, "
> + "but don't reorder instructions",
> + createDefaultMachineSched);
> +
> +/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
> +/// time to do some work.
> +void MachineScheduler::Schedule() {
> + DEBUG(dbgs() << "********** MI Scheduling **********\n");
> + DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
> + SUnits[su].dumpAll(this));
> + // TODO: Put interesting things here.
> +}
> +
> +bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
> + // Initialize the context of the pass.
> + MF = &mf;
> + MLI = &getAnalysis<MachineLoopInfo>();
> + MDT = &getAnalysis<MachineDominatorTree>();
> +
> + // Select the scheduler, or set the default.
> + MachineSchedRegistry::ScheduleDAGCtor Ctor =
> + MachineSchedRegistry::getDefault();
> + if (!Ctor) {
> + Ctor = MachineSchedOpt;
> + MachineSchedRegistry::setDefault(Ctor);
> + }
> + // Instantiate the selected scheduler.
> + OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
> +
> + // Visit all machine basic blocks.
> + for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
> + MBB != MBBEnd; ++MBB) {
> +
> + DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
> + << ":BB#" << MBB->getNumber() << "\n");
> +
> + // Inform ScheduleDAGInstrs of the region being scheduler. It calls back
> + // to our Schedule() method.
> + Scheduler->Run(MBB, MBB->begin(), MBB->end(), MBB->size());
> + }
> + return true;
> +}
> +
> +void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
> + // unimplemented
> +}
> +
> +#ifndef NDEBUG
> +namespace {
> +/// Reorder instructions as much as possible.
> +class InstructionShuffler : public ScheduleDAGInstrs {
> +public:
> + InstructionShuffler(MachineSchedulerPass *P)
> + : ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT)
> + {}
> +
> + /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
> + /// time to do some work.
> + virtual void Schedule() {
> + llvm_unreachable("unimplemented");
> + }
> +};
> +} // namespace
> +
> +static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedulerPass *P) {
> + return new InstructionShuffler(P);
> +}
> +static MachineSchedRegistry ShufflerRegistry("shuffle",
> + "Shuffle machine instructions",
> + createInstructionShuffler);
> +#endif // !NDEBUG
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=148105&r1=148104&r2=148105&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Jan 13 00:30:30 2012
> @@ -129,6 +129,7 @@
> initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
> initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
> initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
> + initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
> initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
> initializeLiveStacksPass(*PassRegistry::getPassRegistry());
> initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
> @@ -148,6 +149,8 @@
> if (StrongPHIElim)
> AU.addRequiredID(StrongPHIEliminationID);
> AU.addRequiredTransitiveID(RegisterCoalescerPassID);
> + if (EnableMachineSched)
> + AU.addRequiredID(MachineSchedulerPassID);
> AU.addRequired<CalculateSpillWeights>();
> AU.addRequired<LiveStacks>();
> AU.addPreserved<LiveStacks>();
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=148105&r1=148104&r2=148105&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Fri Jan 13 00:30:30 2012
> @@ -309,6 +309,7 @@
> initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
> initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
> initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
> + initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
> initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
> initializeLiveStacksPass(*PassRegistry::getPassRegistry());
> initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
> @@ -330,6 +331,8 @@
> if (StrongPHIElim)
> AU.addRequiredID(StrongPHIEliminationID);
> AU.addRequiredTransitiveID(RegisterCoalescerPassID);
> + if (EnableMachineSched)
> + AU.addRequiredID(MachineSchedulerPassID);
> AU.addRequired<CalculateSpillWeights>();
> AU.addRequired<LiveStacks>();
> AU.addPreserved<LiveStacks>();
>
> Modified: llvm/trunk/lib/Target/TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=148105&r1=148104&r2=148105&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/TargetMachine.cpp Fri Jan 13 00:30:30 2012
> @@ -23,6 +23,7 @@
>
> namespace llvm {
> bool StrongPHIElim;
> + bool EnableMachineSched;
> bool HasDivModLibcall;
> bool AsmVerbosityDefault(false);
> }
> @@ -35,7 +36,15 @@
> FunctionSections("ffunction-sections",
> cl::desc("Emit functions into separate sections"),
> cl::init(false));
> -
> +
> +/// EnableMachineSched - temporary flag to enable the machine scheduling pass
> +/// until we complete the register allocation pass configuration cleanup.
> +static cl::opt<bool, true>
> +MachineSchedOpt("enable-misched",
> + cl::desc("Enable the machine instruction scheduling pass."),
> + cl::location(EnableMachineSched),
> + cl::init(false), cl::Hidden);
> +
> //---------------------------------------------------------------------------
> // TargetMachine Class
> //
>
>
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