[llvm-commits] [llvm] r146196 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-shuffle.ll

[Evan Cheng]

On Jan 13, 2012, at 5:23 PM, Chad Rosier wrote:

> Evan,
> One comment below.
> 
> On Dec 8, 2011, at 2:30 PM, Evan Cheng wrote:
> 
>> Author: evancheng
>> Date: Thu Dec  8 16:30:45 2011
>> New Revision: 146196
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=146196&view=rev
>> Log:
>> Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
>> 
>> Modified:
>>   llvm/trunk/lib/Target/X86/X86InstrSSE.td
>>   llvm/trunk/test/CodeGen/X86/avx-shuffle.ll
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=146196&r1=146195&r2=146196&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Dec  8 16:30:45 2011
>> @@ -645,6 +645,16 @@
>>            (VMOVSSrr (v4f32 VR128:$src1),
>>                      (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
>> 
>> +  // 256-bit variants
>> +  def : Pat<(v8i32 (X86Movsd VR256:$src1, VR256:$src2)),
>> +            (SUBREG_TO_REG (i32 0),
>> +                (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
>> +                          (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
>> +  def : Pat<(v8f32 (X86Movsd VR256:$src1, VR256:$src2)),
>> +            (SUBREG_TO_REG (i32 0),
>> +                (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
>> +                          (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
>> +
> 
> Shouldn't the above be using X86Movss and not X86Movsd?

Right, that looks like a pasto. Can you fix it for me?

Thanks,

Evan

> 
> Chad
> 
> 
>>  // Shuffle with VMOVSD
>>  def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
>>            (VMOVSDrr VR128:$src1, FR64:$src2)>;
>> @@ -661,6 +671,17 @@
>>            (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
>>                                                   sub_sd))>;
>> 
>> +  // 256-bit variants
>> +  def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
>> +            (SUBREG_TO_REG (i32 0),
>> +                (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
>> +                          (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
>> +  def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
>> +            (SUBREG_TO_REG (i32 0),
>> +                (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
>> +                          (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
>> +
>> +
>>  // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
>>  // is during lowering, where it's not possible to recognize the fold cause
>>  // it has two uses through a bitcast. One use disappears at isel time and the
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle.ll?rev=146196&r1=146195&r2=146196&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/avx-shuffle.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/avx-shuffle.ll Thu Dec  8 16:30:45 2011
>> @@ -8,3 +8,13 @@
>> ; CHECK: vshufps
>> ; CHECK: vpshufd
>> }
>> +
>> +; rdar://10538417
>> +define <3 x i64> @test2(<3 x i64> %v) nounwind readnone {
>> +; CHECK: test2:
>> +; CHECK: vxorps
>> +; CHECK: vmovsd
>> +  %1 = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef>
>> +  %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
>> +  ret <3 x i64> %2
>> +}
>> 
>> 
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