[llvm-commits] PATCH: Teach the x86 backend to fold mask & shift patterns into an addressing mode computation

[Rotem, Nadav]

I am not familiar with the addressing mode code but I have a few small comments. 


+  // fold (zext (truncate x)) -> (zext x) or
+  //      (zext (truncate x)) -> (truncate x)
+  // This is valid when the truncated bits of x are already zero.
+  // FIXME: We should extend this to work for vectors too.
+  if (N0.getOpcode() == ISD::TRUNCATE && !VT.isVector()) {
+    SDValue Op = N0.getOperand(0);
+    APInt TruncatedBits


Why is this optimization disabled for vectors ?  You can use getScalarSizeInBits and I think that it should work.


+static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
+                                    X86ISelAddressMode &AM) {
+  return true;

Return true ? :)
 
+  // Scale must not be used already.
+  if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) return true;
+
+  SDValue Shift = N;
+  SDValue And = N.getOperand(0);
+  if (N.getOpcode() != ISD::SRL)
+    std::swap(Shift, And);
+  if (Shift.getOpcode() != ISD::SRL || And.getOpcode() != ISD::AND ||
+      !isa<ConstantSDNode>(Shift.getOperand(1)) ||
+      !isa<ConstantSDNode>(And.getOperand(1)))
+    return true;
+  SDValue X = N == Shift ? And.getOperand(0) : Shift.getOperand(0);

Can you add parenthesis here ?

+  unsigned ShiftAmt = Shift.getConstantOperandVal(1);
+  unsigned MaskLZ = CountLeadingZeros_64(Mask);
+  unsigned MaskTZ = CountTrailingZeros_64(Mask);
+
+  // The amount of shift we're trying ot fit into the addressing mode is taken

Typo ot -> to.

+  }
+  SDValue NewShiftAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);

Please use getShiftAmountTy. 


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