[llvm-commits] [llvm] r147770 - in /llvm/trunk/lib/Target/X86: X86.td X86Subtarget.cpp X86Subtarget.h

[Craig Topper]

Author: ctopper
Date: Mon Jan  9 03:02:13 2012
New Revision: 147770

URL: http://llvm.org/viewvc/llvm-project?rev=147770&view=rev
Log:
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.

Modified:
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
    llvm/trunk/lib/Target/X86/X86Subtarget.h

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=147770&r1=147769&r2=147770&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Mon Jan  9 03:02:13 2012
@@ -80,9 +80,10 @@
                                       "Support SSE 4a instructions",
                                       [FeatureSSE3]>;
 
-def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
-                                      "Enable AVX instructions">;
-def FeatureAVX2    : SubtargetFeature<"avx2", "HasAVX2", "true",
+def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
+                                      "Enable AVX instructions",
+                                      [FeatureSSE42]>;
+def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
                                       "Enable AVX2 instructions",
                                       [FeatureAVX]>;
 def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=147770&r1=147769&r2=147770&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Jan  9 03:02:13 2012
@@ -198,7 +198,7 @@
   if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
   if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
   // FIXME: AVX codegen support is not ready.
-  //if ((ECX >> 28) & 1) { HasAVX = true;  ToggleFeature(X86::FeatureAVX); }
+  //if ((ECX >> 28) & 1) { X86SSELevel = AVX;  ToggleFeature(X86::FeatureAVX); }
 
   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
@@ -295,7 +295,7 @@
       }
       // FIXME: AVX2 codegen support is not ready.
       //if ((EBX >> 5) & 0x1) {
-      //  HasAVX2 = true;
+      //  X86SSELevel = AVX2;;
       //  ToggleFeature(X86::FeatureAVX2);
       //}
       if ((EBX >> 8) & 0x1) {
@@ -317,8 +317,6 @@
   , HasX86_64(false)
   , HasPOPCNT(false)
   , HasSSE4A(false)
-  , HasAVX(false)
-  , HasAVX2(false)
   , HasAES(false)
   , HasCLMUL(false)
   , HasFMA3(false)
@@ -372,7 +370,7 @@
       HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
       HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
 
-      if (!HasAVX && X86SSELevel < SSE2) {
+      if (X86SSELevel < SSE2) {
         X86SSELevel = SSE2;
         ToggleFeature(X86::FeatureSSE1);
         ToggleFeature(X86::FeatureSSE2);
@@ -385,9 +383,6 @@
   if (In64BitMode)
     ToggleFeature(X86::Mode64Bit);
 
-  if (HasAVX)
-    X86SSELevel = MMX;
-    
   DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
                << ", 3DNowLevel " << X863DNowLevel
                << ", 64bit " << HasX86_64 << "\n");

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=147770&r1=147769&r2=147770&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Jan  9 03:02:13 2012
@@ -42,7 +42,7 @@
 class X86Subtarget : public X86GenSubtargetInfo {
 protected:
   enum X86SSEEnum {
-    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42
+    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
   };
 
   enum X863DNowEnum {
@@ -75,12 +75,6 @@
   /// HasSSE4A - True if the processor supports SSE4A instructions.
   bool HasSSE4A;
 
-  /// HasAVX - Target has AVX instructions
-  bool HasAVX;
-
-  /// HasAVX2 - Target has AVX2 instructions
-  bool HasAVX2;
-
   /// HasAES - Target has AES instructions
   bool HasAES;
 
@@ -179,24 +173,24 @@
 
   bool hasCMov() const { return HasCMov; }
   bool hasMMX() const { return X86SSELevel >= MMX; }
-  bool hasSSE1() const { return X86SSELevel >= SSE1; }
-  bool hasSSE2() const { return X86SSELevel >= SSE2; }
-  bool hasSSE3() const { return X86SSELevel >= SSE3; }
-  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
-  bool hasSSE41() const { return X86SSELevel >= SSE41; }
-  bool hasSSE42() const { return X86SSELevel >= SSE42; }
+  bool hasSSE1() const { return X86SSELevel >= SSE1 && !hasAVX(); }
+  bool hasSSE2() const { return X86SSELevel >= SSE2 && !hasAVX(); }
+  bool hasSSE3() const { return X86SSELevel >= SSE3 && !hasAVX(); }
+  bool hasSSSE3() const { return X86SSELevel >= SSSE3 && !hasAVX(); }
+  bool hasSSE41() const { return X86SSELevel >= SSE41 && !hasAVX(); }
+  bool hasSSE42() const { return X86SSELevel >= SSE42 && !hasAVX(); }
   bool hasSSE4A() const { return HasSSE4A; }
   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
   bool hasPOPCNT() const { return HasPOPCNT; }
-  bool hasAVX() const { return HasAVX; }
-  bool hasAVX2() const { return HasAVX2; }
-  bool hasXMM() const { return hasSSE1() || hasAVX(); }
-  bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
-  bool hasSSE3orAVX() const { return hasSSE3() || hasAVX(); }
-  bool hasSSSE3orAVX() const { return hasSSSE3() || hasAVX(); }
-  bool hasSSE41orAVX() const { return hasSSE41() || hasAVX(); }
-  bool hasSSE42orAVX() const { return hasSSE42() || hasAVX(); }
+  bool hasAVX() const { return X86SSELevel >= AVX; }
+  bool hasAVX2() const { return X86SSELevel >= AVX2; }
+  bool hasXMM() const { return X86SSELevel >= SSE1; }
+  bool hasXMMInt() const { return X86SSELevel >= SSE2; }
+  bool hasSSE3orAVX() const { return X86SSELevel >= SSE3; }
+  bool hasSSSE3orAVX() const { return X86SSELevel >= SSSE3; }
+  bool hasSSE41orAVX() const { return X86SSELevel >= SSE41; }
+  bool hasSSE42orAVX() const { return X86SSELevel >= SSE42; }
   bool hasAES() const { return HasAES; }
   bool hasCLMUL() const { return HasCLMUL; }
   bool hasFMA3() const { return HasFMA3; }