[llvm-commits] [llvm] r147704 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/inline-asm-q-regs.ll

[Eric Christopher]

Author: echristo
Date: Fri Jan  6 19:02:09 2012
New Revision: 147704

URL: http://llvm.org/viewvc/llvm-project?rev=147704&view=rev
Log:
Make the 'x' constraint work for AVX registers as well.

Fixes rdar://10614894

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147704&r1=147703&r2=147704&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jan  6 19:02:09 2012
@@ -15098,7 +15098,8 @@
       break;
   case 'x':
   case 'Y':
-    if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
+    if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) ||
+        ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
       weight = CW_Register;
     break;
   case 'I':
@@ -15378,8 +15379,8 @@
     case 'Y':   // SSE_REGS if SSE2 allowed
       if (!Subtarget->hasXMMInt()) break;
       // FALL THROUGH.
-    case 'x':   // SSE_REGS if SSE1 allowed
-      if (!Subtarget->hasXMM()) break;
+    case 'x':   // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
+      if (!Subtarget->hasXMM() && !Subtarget->hasAVX()) break;
 
       switch (VT.getSimpleVT().SimpleTy) {
       default: break;
@@ -15398,6 +15399,15 @@
       case MVT::v4f32:
       case MVT::v2f64:
         return std::make_pair(0U, X86::VR128RegisterClass);
+      // AVX types.
+      case MVT::v32i8:
+      case MVT::v16i16:
+      case MVT::v8i32:
+      case MVT::v4i64:
+      case MVT::v8f32:
+      case MVT::v4f64:
+        return std::make_pair(0U, X86::VR256RegisterClass);
+        
       }
       break;
     }

Modified: llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll?rev=147704&r1=147703&r2=147704&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll Fri Jan  6 19:02:09 2012
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 -mattr=+avx
 ; rdar://7066579
 
 	%0 = type { i64, i64, i64, i64, i64 }		; type %0
@@ -27,3 +27,11 @@
   %0 = tail call { i8, i8, i8, i8, i8 } asm "foo $1, $2, $3, $4, $1\0Axchgb ${0:b}, ${0:h}", "=q,={ax},={bx},={cx},={dx},0,1,2,3,4,~{dirflag},~{fpsr},~{flags}"(i8 %val, i8 %a, i8 %b, i8 %c, i8 %d) nounwind
   ret void
 }
+
+; rdar://10614894
+define <8 x float> @test5(<8 x float> %a, <8 x float> %b) nounwind {
+entry:
+  %0 = tail call <8 x float> asm "vperm2f128 $3, $2, $1, $0", "=x,x,x,i,~{dirflag},~{fpsr},~{flags}"(<8 x float> %a, <8 x float> %b, i32 16) nounwind
+  ret <8 x float> %0
+}
+