[llvm-commits] [llvm] r147426 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-12-28-vselecti8.ll test/CodeGen/X86/sext-blend.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse41-blend.ll

[Nadav Rotem]

Author: nadav
Date: Mon Jan  2 02:05:46 2012
New Revision: 147426

URL: http://llvm.org/viewvc/llvm-project?rev=147426&view=rev
Log:

Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit.


Added:
    llvm/trunk/test/CodeGen/X86/sext-blend.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll
    llvm/trunk/test/CodeGen/X86/sse2-blend.ll
    llvm/trunk/test/CodeGen/X86/sse41-blend.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147426&r1=147425&r2=147426&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan  2 02:05:46 2012
@@ -13133,6 +13133,24 @@
       }
   }
 
+  // The VSELECT instruction is lowered to SSE blend instructions. In many cases
+  // the mask is sign-extended to fill the entire lane. However, we only care
+  // for the highest bit. Convert sign_extend to srl because it is cheaper.
+  // (vselect(sign_extend(x))) ->  vselect(srl(x))
+  if (N->getOpcode() == ISD::VSELECT &&
+      Cond.getOpcode() == ISD::SIGN_EXTEND_INREG && Cond.hasOneUse()) {
+    EVT CondVT = Cond.getValueType();
+    EVT SExtTy = cast<VTSDNode>(Cond.getOperand(1))->getVT();
+    unsigned BitsDiff = CondVT.getScalarType().getSizeInBits() -
+                        SExtTy.getScalarType().getSizeInBits();
+
+    EVT ShiftType = EVT::getVectorVT(*DAG.getContext(),
+                MVT::i32, CondVT.getVectorNumElements());
+    SDValue SHL = DAG.getNode(ISD::SHL, DL, CondVT, Cond.getOperand(0),
+                DAG.getConstant(BitsDiff, ShiftType));
+    return DAG.getNode(ISD::VSELECT, DL, VT, SHL, LHS, RHS);
+  }
+
   return SDValue();
 }
 

Modified: llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll?rev=147426&r1=147425&r2=147426&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll Mon Jan  2 02:05:46 2012
@@ -5,8 +5,10 @@
 
 ; CHECK: @foo8
 ; CHECK: psll
-; CHECK: psraw
-; CHECK: pblendvb
+; CHECK-NOT: sra
+; CHECK: pandn
+; CHECK: pand
+; CHECK: or
 ; CHECK: ret
 define void @foo8(float* nocapture %RET) nounwind {
 allocas:

Added: llvm/trunk/test/CodeGen/X86/sext-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-blend.ll?rev=147426&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sext-blend.ll (added)
+++ llvm/trunk/test/CodeGen/X86/sext-blend.ll Mon Jan  2 02:05:46 2012
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s
+
+; CHECK: foo
+define <4 x double> @foo(<4 x double> %x, <4 x double> %y) {
+  ; CHECK: cmpnlepd
+  ; CHECK: psllq
+  ; CHECK-NEXT: blendvpd
+  ; CHECK: psllq
+  ; CHECK-NEXT: blendvpd
+  ; CHECK: ret
+  %min_is_x = fcmp ult <4 x double> %x, %y
+  %min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y
+  ret <4 x double> %min
+}
+

Modified: llvm/trunk/test/CodeGen/X86/sse2-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-blend.ll?rev=147426&r1=147425&r2=147426&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-blend.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-blend.ll Mon Jan  2 02:05:46 2012
@@ -28,10 +28,10 @@
 
 ; Without forcing instructions, fall back to the preferred PS domain.
 ; CHECK: vsel_i64
-; CHECK: xorps
-; CHECK: andps
-; CHECK: andnps
-; CHECK: orps
+; CHECK: pxor
+; CHECK: and
+; CHECK: andn
+; CHECK: or
 ; CHECK: ret
 
 define void at vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) {
@@ -44,10 +44,10 @@
 
 ; Without forcing instructions, fall back to the preferred PS domain.
 ; CHECK: vsel_double
-; CHECK: xorps
-; CHECK: andps
-; CHECK: andnps
-; CHECK: orps
+; CHECK: xor
+; CHECK: and
+; CHECK: andn
+; CHECK: or
 ; CHECK: ret
 
 define void at vsel_double(<4 x double>* %v1, <4 x double>* %v2) {

Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=147426&r1=147425&r2=147426&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Mon Jan  2 02:05:46 2012
@@ -36,6 +36,7 @@
 
 
 ;CHECK: vsel_double
+;CHECK-NOT: sra
 ;CHECK: blendvpd
 ;CHECK: ret
 define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
@@ -54,6 +55,7 @@
 
 
 ;CHECK: vsel_i8
+;CHECK-NOT: sra
 ;CHECK: pblendvb
 ;CHECK: ret
 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
@@ -65,6 +67,7 @@
 ; CHECK: A
 define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
   ; CHECK: cmplepd
+  ; CHECK-NOT: sra
   ; CHECK: blendvpd
   %max_is_x = fcmp oge <2 x double> %x, %y
   %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
@@ -74,6 +77,7 @@
 ; CHECK: B
 define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
   ; CHECK: cmpnlepd
+  ; CHECK-NOT: sra
   ; CHECK: blendvpd
   %min_is_x = fcmp ult <2 x double> %x, %y
   %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y