[llvm-commits] [llvm] r147366 - in /llvm/trunk/lib/Target/X86: MCTargetDesc/X86BaseInfo.h MCTargetDesc/X86MCCodeEmitter.cpp X86InstrFMA.td X86InstrFormats.td X86InstrXOP.td
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Fri Dec 30 13:21:50 PST 2011
On Fri, Dec 30, 2011 at 2:48 AM, Craig Topper <craig.topper at gmail.com> wrote:
> Author: ctopper
> Date: Thu Dec 29 22:48:54 2011
> New Revision: 147366
>
> URL: http://llvm.org/viewvc/llvm-project?rev=147366&view=rev
> Log:
> Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
>
> Modified:
> llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> llvm/trunk/lib/Target/X86/X86InstrFMA.td
> llvm/trunk/lib/Target/X86/X86InstrFormats.td
> llvm/trunk/lib/Target/X86/X86InstrXOP.td
>
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h?rev=147366&r1=147365&r2=147366&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h Thu Dec 29 22:48:54 2011
> @@ -426,10 +426,9 @@
> /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
> Has3DNow0F0FOpcode = 1U << 7,
>
> - /// XOP_W - Same bit as VEX_W. Used to indicate swapping of
> - /// operand 3 and 4 to be encoded in ModRM or I8IMM. This is used
> - /// for FMA4 and XOP instructions.
> - XOP_W = 1U << 8,
> + /// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in
> + /// ModRM or I8IMM. This is used for FMA4 and XOP instructions.
> + MemOp4 = 1U << 8,
Given the comment, maybe this should be a more descriptive instead:
what about SwpMemImmOp4? or something like that...
> /// XOP - Opcode prefix used by XOP instructions.
> XOP = 1U << 9
> @@ -503,11 +502,11 @@
> return 0;
> case X86II::MRMSrcMem: {
> bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
> - bool HasXOP_W = (TSFlags >> X86II::VEXShift) & X86II::XOP_W;
> + bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
> unsigned FirstMemOp = 1;
> if (HasVEX_4V)
> ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
> - if (HasXOP_W)
> + if (HasMemOp4)
> ++FirstMemOp;// Skip the register source (which is encoded in I8IMM).
>
> // FIXME: Maybe lea should have its own form? This is a horrible hack.
>
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=147366&r1=147365&r2=147366&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Thu Dec 29 22:48:54 2011
> @@ -431,10 +431,6 @@
> // opcode extension, or ignored, depending on the opcode byte)
> unsigned char VEX_W = 0;
>
> - // XOP_W: opcode specific, same bit as VEX_W, but used to
> - // swap operand 3 and 4 for FMA4 and XOP instructions
> - unsigned char XOP_W = 0;
> -
> // XOP: Use XOP prefix byte 0x8f instead of VEX.
> unsigned char XOP = 0;
>
> @@ -477,9 +473,6 @@
> if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
> VEX_W = 1;
>
> - if ((TSFlags >> X86II::VEXShift) & X86II::XOP_W)
> - XOP_W = 1;
> -
> if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
> XOP = 1;
>
> @@ -669,7 +662,7 @@
> // 3 byte VEX prefix
> EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
> EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
> - EmitByte(LastByte | ((VEX_W | XOP_W) << 7), CurByte, OS);
> + EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
> }
>
> /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
> @@ -929,8 +922,8 @@
> // It uses the VEX.VVVV field?
> bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
> bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
> - bool HasXOP_W = (TSFlags >> X86II::VEXShift) & X86II::XOP_W;
> - unsigned XOP_W_I8IMMOperand = 2;
> + bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
> + const unsigned MemOp4_I8IMMOperand = 2;
>
> // Determine where the memory operand starts, if present.
> int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
> @@ -1003,14 +996,14 @@
> if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
> SrcRegNum++;
>
> - if(HasXOP_W) // Skip 2nd src (which is encoded in I8IMM)
> + if(HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
> SrcRegNum++;
>
> EmitRegModRMByte(MI.getOperand(SrcRegNum),
> GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
>
> - // 2 operands skipped with HasXOP_W, comensate accordingly
> - CurOp = HasXOP_W ? SrcRegNum : SrcRegNum + 1;
> + // 2 operands skipped with HasMemOp4, comensate accordingly
> + CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
> if (HasVEX_4VOp3)
> ++CurOp;
> break;
> @@ -1022,7 +1015,7 @@
> ++AddrOperands;
> ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
> }
> - if(HasXOP_W) // Skip second register source (encoded in I8IMM)
> + if(HasMemOp4) // Skip second register source (encoded in I8IMM)
> ++FirstMemOp;
>
> EmitByte(BaseOpcode, CurByte, OS);
> @@ -1113,7 +1106,7 @@
> // The last source register of a 4 operand instruction in AVX is encoded
> // in bits[7:4] of a immediate byte.
> if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
> - const MCOperand &MO = MI.getOperand(HasXOP_W ? XOP_W_I8IMMOperand
> + const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
> : CurOp);
> CurOp++;
> bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg());
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=147366&r1=147365&r2=147366&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFMA.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFMA.td Thu Dec 29 22:48:54 2011
> @@ -105,13 +105,13 @@
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
> [(set VR128:$dst,
> - (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_W;
> + (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
> def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
> (ins VR128:$src1, VR128:$src2, memop:$src3),
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
> [(set VR128:$dst,
> - (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, XOP_W;
> + (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
> def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
> (ins VR128:$src1, memop:$src2, VR128:$src3),
> !strconcat(OpcodeStr,
> @@ -128,13 +128,13 @@
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
> [(set VR128:$dst,
> - (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_W;
> + (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
> def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
> (ins VR128:$src1, VR128:$src2, f128mem:$src3),
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
> [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
> - (ld_frag128 addr:$src3)))]>, XOP_W;
> + (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
> def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
> (ins VR128:$src1, f128mem:$src2, VR128:$src3),
> !strconcat(OpcodeStr,
> @@ -146,13 +146,13 @@
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
> [(set VR256:$dst,
> - (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, XOP_W;
> + (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
> def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
> (ins VR256:$src1, VR256:$src2, f256mem:$src3),
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
> [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
> - (ld_frag256 addr:$src3)))]>, XOP_W;
> + (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
> def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
> (ins VR256:$src1, f256mem:$src2, VR256:$src3),
> !strconcat(OpcodeStr,
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=147366&r1=147365&r2=147366&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Thu Dec 29 22:48:54 2011
> @@ -120,7 +120,7 @@
> class VEX_L { bit hasVEX_L = 1; }
> class VEX_LIG { bit ignoresVEX_L = 1; }
> class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
> -class XOP_W { bit hasXOP_WPrefix = 1; }
> +class MemOp4 { bit hasMemOp4Prefix = 1; }
> class XOP { bit hasXOP_Prefix = 1; }
> class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
> string AsmStr, Domain d = GenericDomain>
> @@ -161,7 +161,7 @@
> bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
> bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
> bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
> - bit hasXOP_WPrefix = 0; // Same bit as VEX_W, but used for swapping operands
> + bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
> bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
>
> // TSFlags layout should be kept in sync with X86InstrInfo.h.
> @@ -184,7 +184,7 @@
> let TSFlags{38} = hasVEX_L;
> let TSFlags{39} = ignoresVEX_L;
> let TSFlags{40} = has3DNow0F0FOpcode;
> - let TSFlags{41} = hasXOP_WPrefix;
> + let TSFlags{41} = hasMemOp4Prefix;
> let TSFlags{42} = hasXOP_Prefix;
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrXOP.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrXOP.td?rev=147366&r1=147365&r2=147366&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrXOP.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrXOP.td Thu Dec 29 22:48:54 2011
> @@ -169,7 +169,7 @@
> (ins VR128:$src1, VR128:$src2, f128mem:$src3),
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
> - []>, VEX_4V, VEX_I8IMM, XOP_W;
> + []>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
> def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
> (ins VR128:$src1, f128mem:$src2, VR128:$src3),
> !strconcat(OpcodeStr,
> @@ -192,7 +192,7 @@
> (ins VR256:$src1, VR256:$src2, f256mem:$src3),
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
> - []>, VEX_4V, VEX_I8IMM, XOP_W;
> + []>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
> def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
> (ins VR256:$src1, f256mem:$src2, VR256:$src3),
> !strconcat(OpcodeStr,
> @@ -214,7 +214,7 @@
> (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
> !strconcat(OpcodeStr,
> "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
> - []>, XOP_W;
> + []>, VEX_W, MemOp4;
> def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
> (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
> !strconcat(OpcodeStr,
> @@ -229,7 +229,7 @@
> (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
> !strconcat(OpcodeStr,
> "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
> - []>, XOP_W;
> + []>, VEX_W, MemOp4;
> def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
> (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
> !strconcat(OpcodeStr,
>
>
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--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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