[llvm-commits] [llvm] r147359 - in /llvm/trunk: lib/Target/PowerPC/PPCFrameLowering.cpp lib/Target/PowerPC/PPCRegisterInfo.cpp test/CodeGen/PowerPC/2010-02-12-saveCR.ll test/CodeGen/PowerPC/Frames-large.ll
Hal Finkel
hfinkel at anl.gov
Thu Dec 29 16:34:00 PST 2011
Author: hfinkel
Date: Thu Dec 29 18:34:00 2011
New Revision: 147359
URL: http://llvm.org/viewvc/llvm-project?rev=147359&view=rev
Log:
Cleanup stack/frame register define/kill states. This fixes two bugs:
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).
2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=147359&r1=147358&r2=147359&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Thu Dec 29 18:34:00 2011
@@ -367,8 +367,8 @@
.addReg(PPC::R0, RegState::Kill)
.addImm(NegFrameSize);
BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
- .addReg(PPC::R1)
- .addReg(PPC::R1)
+ .addReg(PPC::R1, RegState::Kill)
+ .addReg(PPC::R1, RegState::Define)
.addReg(PPC::R0);
} else if (isInt<16>(NegFrameSize)) {
BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
@@ -382,8 +382,8 @@
.addReg(PPC::R0, RegState::Kill)
.addImm(NegFrameSize & 0xFFFF);
BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
- .addReg(PPC::R1)
- .addReg(PPC::R1)
+ .addReg(PPC::R1, RegState::Kill)
+ .addReg(PPC::R1, RegState::Define)
.addReg(PPC::R0);
}
} else { // PPC64.
@@ -400,8 +400,8 @@
.addReg(PPC::X0)
.addImm(NegFrameSize);
BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
- .addReg(PPC::X1)
- .addReg(PPC::X1)
+ .addReg(PPC::X1, RegState::Kill)
+ .addReg(PPC::X1, RegState::Define)
.addReg(PPC::X0);
} else if (isInt<16>(NegFrameSize)) {
BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
@@ -415,8 +415,8 @@
.addReg(PPC::X0, RegState::Kill)
.addImm(NegFrameSize & 0xFFFF);
BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
- .addReg(PPC::X1)
- .addReg(PPC::X1)
+ .addReg(PPC::X1, RegState::Kill)
+ .addReg(PPC::X1, RegState::Define)
.addReg(PPC::X0);
}
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=147359&r1=147358&r2=147359&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Dec 29 18:34:00 2011
@@ -299,8 +299,9 @@
DebugLoc dl = MI->getDebugLoc();
if (isInt<16>(CalleeAmt)) {
- BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
- addImm(CalleeAmt);
+ BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
+ .addReg(StackReg, RegState::Kill)
+ .addImm(CalleeAmt);
} else {
MachineBasicBlock::iterator MBBI = I;
BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
@@ -308,9 +309,8 @@
BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
.addReg(TmpReg, RegState::Kill)
.addImm(CalleeAmt & 0xFFFF);
- BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
- .addReg(StackReg)
- .addReg(StackReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
+ .addReg(StackReg, RegState::Kill)
.addReg(TmpReg);
}
}
@@ -407,12 +407,12 @@
if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
.addReg(Reg, RegState::Kill)
- .addReg(PPC::X1)
+ .addReg(PPC::X1, RegState::Define)
.addReg(MI.getOperand(1).getReg());
else
BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
.addReg(PPC::X0, RegState::Kill)
- .addReg(PPC::X1)
+ .addReg(PPC::X1, RegState::Define)
.addReg(MI.getOperand(1).getReg());
if (!MI.getOperand(1).isKill())
@@ -428,7 +428,7 @@
} else {
BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
.addReg(Reg, RegState::Kill)
- .addReg(PPC::R1)
+ .addReg(PPC::R1, RegState::Define)
.addReg(MI.getOperand(1).getReg());
if (!MI.getOperand(1).isKill())
@@ -681,7 +681,7 @@
unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
- MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
+ MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
}
unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Modified: llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll?rev=147359&r1=147358&r2=147359&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll Thu Dec 29 18:34:00 2011
@@ -6,16 +6,22 @@
define void @foo() nounwind {
entry:
+;CHECK: mfcr r2
;CHECK: lis r3, 1
+;CHECK: rlwinm r2, r2, 8, 0, 31
;CHECK: ori r3, r3, 34524
+;CHECK: stwx r2, r1, r3
+; Make sure that the register scavenger returns the same temporary register.
;CHECK: mfcr r2
-;CHECK: rlwinm r2, r2, 8, 0, 31
+;CHECK: lis r3, 1
+;CHECK: rlwinm r2, r2, 12, 0, 31
+;CHECK: ori r3, r3, 34520
;CHECK: stwx r2, r1, r3
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
call void @bar(i8* %x1) nounwind
- call void asm sideeffect "", "~{cr2}"() nounwind
+ call void asm sideeffect "", "~{cr2},~{cr3}"() nounwind
br label %return
return: ; preds = %entry
Modified: llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll?rev=147359&r1=147358&r2=147359&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll Thu Dec 29 18:34:00 2011
@@ -15,9 +15,9 @@
; PPC32-NOFP: _f1:
; PPC32-NOFP: lis r0, -1
-; PPC32-NOFP: addi r3, r1, 68
; PPC32-NOFP: ori r0, r0, 32704
; PPC32-NOFP: stwux r1, r1, r0
+; PPC32-NOFP: addi r3, r1, 68
; PPC32-NOFP: lwz r1, 0(r1)
; PPC32-NOFP: blr
@@ -25,10 +25,10 @@
; PPC32-FP: _f1:
; PPC32-FP: lis r0, -1
; PPC32-FP: stw r31, -4(r1)
-; PPC32-FP: mr r31, r1
; PPC32-FP: ori r0, r0, 32704
-; PPC32-FP: addi r3, r31, 64
; PPC32-FP: stwux r1, r1, r0
+; PPC32-FP: mr r31, r1
+; PPC32-FP: addi r3, r31, 64
; PPC32-FP: lwz r1, 0(r1)
; PPC32-FP: lwz r31, -4(r1)
; PPC32-FP: blr
@@ -36,9 +36,9 @@
; PPC64-NOFP: _f1:
; PPC64-NOFP: lis r0, -1
-; PPC64-NOFP: addi r3, r1, 116
; PPC64-NOFP: ori r0, r0, 32656
; PPC64-NOFP: stdux r1, r1, r0
+; PPC64-NOFP: addi r3, r1, 116
; PPC64-NOFP: ld r1, 0(r1)
; PPC64-NOFP: blr
@@ -46,10 +46,10 @@
; PPC64-FP: _f1:
; PPC64-FP: lis r0, -1
; PPC64-FP: std r31, -8(r1)
-; PPC64-FP: mr r31, r1
; PPC64-FP: ori r0, r0, 32640
-; PPC64-FP: addi r3, r31, 124
; PPC64-FP: stdux r1, r1, r0
+; PPC64-FP: mr r31, r1
+; PPC64-FP: addi r3, r31, 124
; PPC64-FP: ld r1, 0(r1)
; PPC64-FP: ld r31, -8(r1)
; PPC64-FP: blr
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