[llvm-commits] [llvm] r147289 - in /llvm/trunk/lib/Target: Hexagon/HexagonExpandPredSpillCode.cpp Hexagon/HexagonInstrInfo.cpp Hexagon/HexagonRegisterInfo.cpp PTX/PTXMFInfoExtract.cpp

[Benjamin Kramer]

Author: d0k
Date: Tue Dec 27 05:41:05 2011
New Revision: 147289

URL: http://llvm.org/viewvc/llvm-project?rev=147289&view=rev
Log:
Clean up some Release build warnings.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
    llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp?rev=147289&r1=147288&r2=147289&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp Tue Dec 27 05:41:05 2011
@@ -70,7 +70,6 @@
 bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
 
   const HexagonInstrInfo *TII = QTM.getInstrInfo();
-  const HexagonRegisterInfo *RegInfo = QTM.getRegisterInfo();
 
   // Loop over all of the basic blocks.
   for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
@@ -84,7 +83,7 @@
       if (Opc == Hexagon::STriw_pred) {
         // STriw_pred [R30], ofst, SrcReg;
         unsigned FP = MI->getOperand(0).getReg();
-        assert(FP == RegInfo->getFrameRegister() &&
+        assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
                "Not a Frame Pointer, Nor a Spill Slot");
         assert(MI->getOperand(1).isImm() && "Not an offset");
         int Offset = MI->getOperand(1).getImm();
@@ -129,7 +128,7 @@
         assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
                "Not a predicate register");
         unsigned FP = MI->getOperand(1).getReg();
-        assert(FP == RegInfo->getFrameRegister() &&
+        assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
                "Not a Frame Pointer, Nor a Spill Slot");
         assert(MI->getOperand(2).isImm() && "Not an offset");
         int Offset = MI->getOperand(2).getImm();

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=147289&r1=147288&r2=147289&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Dec 27 05:41:05 2011
@@ -461,7 +461,7 @@
   } else if (VT == MVT::i64) {
     TRC =  Hexagon::DoubleRegsRegisterClass;
   } else {
-    assert(0 && "Cannot handle this register class");
+    llvm_unreachable("Cannot handle this register class");
   }
 
   unsigned NewReg = RegInfo.createVirtualRegister(TRC);
@@ -553,10 +553,6 @@
 
   case Hexagon::JMPR:
     return false;
-    return true;
-
-  default:
-    return true;
   }
 
   return true;
@@ -793,9 +789,8 @@
   case Hexagon::DEALLOC_RET_V4:
     return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
                               Hexagon::DEALLOC_RET_cNotPt_V4;
-  default:
-    assert(false && "Unexpected predicable instruction");
   }
+  llvm_unreachable("Unexpected predicable instruction");
 }
 
 
@@ -1243,8 +1238,8 @@
     return true;
   }
 
-  assert(0 && "No offset range is defined for this opcode. Please define it in \
-               the above switch statement!");
+  llvm_unreachable("No offset range is defined for this opcode. "
+                   "Please define it in the above switch statement!");
 }
 
 

Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=147289&r1=147288&r2=147289&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Tue Dec 27 05:41:05 2011
@@ -58,18 +58,16 @@
   };
 
   switch(Subtarget.getHexagonArchVersion()) {
+  case HexagonSubtarget::V1:
+    break;
   case HexagonSubtarget::V2:
     return CalleeSavedRegsV2;
-    break;
   case HexagonSubtarget::V3:
   case HexagonSubtarget::V4:
     return CalleeSavedRegsV3;
-    break;
-  default:
-    const char *ErrorString = 
-      "Callee saved registers requested for unknown archtecture version";
-    llvm_unreachable(ErrorString);
   }
+  llvm_unreachable("Callee saved registers requested for unknown architecture "
+                   "version");
 }
 
 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
@@ -106,18 +104,16 @@
   };
 
   switch(Subtarget.getHexagonArchVersion()) {
+  case HexagonSubtarget::V1:
+    break;
   case HexagonSubtarget::V2:
     return CalleeSavedRegClassesV2;
-    break;
   case HexagonSubtarget::V3:
   case HexagonSubtarget::V4:
     return CalleeSavedRegClassesV3;
-    break;
-  default:
-    const char *ErrorString = 
-      "Callee saved register classes requested for unknown archtecture version";
-    llvm_unreachable(ErrorString);
   }
+  llvm_unreachable("Callee saved register classes requested for unknown "
+                   "architecture version");
 }
 
 void HexagonRegisterInfo::

Modified: llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp?rev=147289&r1=147288&r2=147289&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp Tue Dec 27 05:41:05 2011
@@ -71,6 +71,8 @@
       RegType = PTXRegisterType::F32;
     else if (TRC == PTX::RegF64RegisterClass)
       RegType = PTXRegisterType::F64;
+    else
+      llvm_unreachable("Unkown register class.");
     MFI->addRegister(Reg, RegType, PTXRegisterSpace::Reg);
   }