[llvm-commits] [llvm] r147170 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

[Jim Grosbach]

Author: grosbach
Date: Thu Dec 22 13:55:21 2011
New Revision: 147170

URL: http://llvm.org/viewvc/llvm-project?rev=147170&view=rev
Log:
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.

The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=147170&r1=147169&r2=147170&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Dec 22 13:55:21 2011
@@ -1594,8 +1594,11 @@
                 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
                 list<dag> pattern>
   : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
+  bits<5> fbits;
   // size (fixed-point number): sx == 0 ? 16 : 32
   let Inst{7} = op5; // sx
+  let Inst{5} = fbits{0};
+  let Inst{3-0} = fbits{4-1};
 }
 
 // VFP conversion instructions, if no NEON