[llvm-commits] [llvm] r147022 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/mips64countleading.ll

Akira Hatanaka ahatanaka at mips.com
Tue Dec 20 16:20:28 PST 2011


Author: ahatanak
Date: Tue Dec 20 18:20:27 2011
New Revision: 147022

URL: http://llvm.org/viewvc/llvm-project?rev=147022&view=rev
Log:
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
case for DCLO and DCLZ.

Added:
    llvm/trunk/test/CodeGen/Mips/mips64countleading.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147022&r1=147021&r2=147022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 18:20:27 2011
@@ -222,8 +222,10 @@
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
   }
 
-  if (!Subtarget->hasBitCount())
+  if (!Subtarget->hasBitCount()) {
     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
+    setOperationAction(ISD::CTLZ, MVT::i64, Expand);
+  }
 
   if (!Subtarget->hasSwap()) {
     setOperationAction(ISD::BSWAP, MVT::i32, Expand);

Added: llvm/trunk/test/CodeGen/Mips/mips64countleading.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64countleading.ll?rev=147022&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64countleading.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/mips64countleading.ll Tue Dec 20 18:20:27 2011
@@ -0,0 +1,19 @@
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
+
+define i64 @t1(i64 %X) nounwind readnone {
+entry:
+; CHECK: dclz
+  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
+  ret i64 %tmp1
+}
+
+declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
+
+define i64 @t3(i64 %X) nounwind readnone {
+entry:
+; CHECK: dclo 
+  %neg = xor i64 %X, -1
+  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
+  ret i64 %tmp1
+}
+





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