[llvm-commits] [llvm] r146997 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/ARM/fast-isel-deadcode.ll test/CodeGen/Thumb2/aligned-spill.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Tue Dec 20 16:15:04 2011
New Revision: 146997

URL: http://llvm.org/viewvc/llvm-project?rev=146997&view=rev
Log:
Heed spill slot alignment on ARM.

Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

Added:
    llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=146997&r1=146996&r2=146997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Dec 20 16:15:04 2011
@@ -765,7 +765,8 @@
       break;
     case 16:
       if (ARM::QPRRegClass.hasSubClassEq(RC)) {
-        if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
+        // Use aligned spills if the stack can be realigned.
+        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
           AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
                      .addFrameIndex(FI).addImm(16)
                      .addReg(SrcReg, getKillRegState(isKill))
@@ -914,7 +915,7 @@
     break;
   case 16:
     if (ARM::QPRRegClass.hasSubClassEq(RC)) {
-      if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
+      if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
         AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
                      .addFrameIndex(FI).addImm(16)
                      .addMemOperand(MMO));

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=146997&r1=146996&r2=146997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Dec 20 16:15:04 2011
@@ -542,7 +542,7 @@
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   const Function *F = MF.getFunction();
   unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
-  bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
+  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
                                F->hasFnAttr(Attribute::StackAlignment));
 
   return requiresRealignment && canRealignStack(MF);

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll?rev=146997&r1=146996&r2=146997&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Tue Dec 20 16:15:04 2011
@@ -15,8 +15,7 @@
 ; THUMB-NOT: sxtb
 ; THUMB: movs r0, #0
 ; THUMB: movt r0, #0
-; THUMB: add sp, #32
-; THUMb: pop {r7, pc}
+; THUMB: pop
   ret i32 0
 }
 

Added: llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll?rev=146997&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Tue Dec 20 16:15:04 2011
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
+target triple = "thumbv7-apple-ios"
+
+; CHECK: f
+; This function is forced to spill a double.
+; Verify that the spill slot is properly aligned.
+;
+; The caller-saved r4 is used as a scratch register for stack realignment.
+; CHECK: push {r4, r7, lr}
+; CHECK: bic r4, r4, #7
+; CHECK: mov sp, r4
+define void @f(double* nocapture %p) nounwind ssp {
+entry:
+  %0 = load double* %p, align 4
+  tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind
+  tail call void @g() nounwind
+  store double %0, double* %p, align 4
+  ret void
+}
+
+declare void @g()