[llvm-commits] [llvm] r146983 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-vld-encoding.s
Jim Grosbach
grosbach at apple.com
Tue Dec 20 11:21:27 PST 2011
Author: grosbach
Date: Tue Dec 20 13:21:26 2011
New Revision: 146983
URL: http://llvm.org/viewvc/llvm-project?rev=146983&view=rev
Log:
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/neon-vld-encoding.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146983&r1=146982&r2=146983&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 20 13:21:26 2011
@@ -174,7 +174,7 @@
let ParserMatchClass = VecListOneDWordIndexAsmOperand;
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
}
-// Register list of two D registers, with byte lane subscripting.
+// Register list of two D registers with byte lane subscripting.
def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
let Name = "VecListTwoDByteIndexed";
let ParserMethod = "parseVectorList";
@@ -204,6 +204,26 @@
let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
}
+// Register list of two Q registers with half-word lane subscripting.
+def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
+ let Name = "VecListTwoQHWordIndexed";
+ let ParserMethod = "parseVectorList";
+ let RenderMethod = "addVecListIndexedOperands";
+}
+def VecListTwoQHWordIndexed : Operand<i32> {
+ let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
+ let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
+}
+// ...with word lane subscripting.
+def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
+ let Name = "VecListTwoQWordIndexed";
+ let ParserMethod = "parseVectorList";
+ let RenderMethod = "addVecListIndexedOperands";
+}
+def VecListTwoQWordIndexed : Operand<i32> {
+ let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
+ let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
+}
//===----------------------------------------------------------------------===//
// NEON-specific DAG Nodes.
@@ -5735,6 +5755,10 @@
(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD2LNqAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
+ (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD2LNqAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
+ (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!",
(ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
@@ -5742,6 +5766,10 @@
(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
+ (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
+ (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VLD2LNdWB_register_Asm :
NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
(ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
@@ -5754,6 +5782,14 @@
NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
(ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
+defm VLD2LNqWB_register_Asm :
+ NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
+ (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
+defm VLD2LNqWB_register_Asm :
+ NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
+ (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
// VST2 single-lane pseudo-instructions. These need special handling for
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146983&r1=146982&r2=146983&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 13:21:26 2011
@@ -1128,33 +1128,49 @@
return VectorList.Count == 2;
}
+ bool isSingleSpacedVectorIndexed() const {
+ return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
+ }
+ bool isDoubleSpacedVectorIndexed() const {
+ return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
+ }
bool isVecListOneDByteIndexed() const {
- if (Kind != k_VectorListIndexed) return false;
+ if (!isSingleSpacedVectorIndexed()) return false;
return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
}
bool isVecListOneDHWordIndexed() const {
- if (Kind != k_VectorListIndexed) return false;
+ if (!isSingleSpacedVectorIndexed()) return false;
return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
}
bool isVecListOneDWordIndexed() const {
- if (Kind != k_VectorListIndexed) return false;
+ if (!isSingleSpacedVectorIndexed()) return false;
return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
}
bool isVecListTwoDByteIndexed() const {
- if (Kind != k_VectorListIndexed) return false;
+ if (!isSingleSpacedVectorIndexed()) return false;
return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
}
bool isVecListTwoDHWordIndexed() const {
- if (Kind != k_VectorListIndexed) return false;
+ if (!isSingleSpacedVectorIndexed()) return false;
+ return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
+ }
+
+ bool isVecListTwoQWordIndexed() const {
+ if (!isDoubleSpacedVectorIndexed()) return false;
+ return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
+ }
+
+ bool isVecListTwoQHWordIndexed() const {
+ if (!isDoubleSpacedVectorIndexed()) return false;
return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
}
bool isVecListTwoDWordIndexed() const {
- if (Kind != k_VectorListIndexed) return false;
+ if (!isSingleSpacedVectorIndexed()) return false;
return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
}
@@ -2035,11 +2051,14 @@
}
static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
- unsigned Index, SMLoc S, SMLoc E) {
+ unsigned Index,
+ bool isDoubleSpaced,
+ SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
Op->VectorList.RegNum = RegNum;
Op->VectorList.Count = Count;
Op->VectorList.LaneIndex = Index;
+ Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
@@ -2849,7 +2868,8 @@
break;
case IndexedLane:
Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
- LaneIndex, S,E));
+ LaneIndex,
+ false, S, E));
break;
}
return MatchOperand_Success;
@@ -2872,7 +2892,8 @@
break;
case IndexedLane:
Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
- LaneIndex, S,E));
+ LaneIndex,
+ false, S, E));
break;
}
return MatchOperand_Success;
@@ -3020,11 +3041,6 @@
Error(EndLoc, "mismatched lane index in register list");
return MatchOperand_ParseFail;
}
- if (Spacing == 2 && LaneKind != NoLanes) {
- Error(EndLoc,
- "lane index specfier invalid in double spaced register list");
- return MatchOperand_ParseFail;
- }
}
SMLoc E = Parser.getTok().getLoc();
@@ -3047,7 +3063,9 @@
break;
case IndexedLane:
Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
- LaneIndex, S, E));
+ LaneIndex,
+ (Spacing == 2),
+ S, E));
break;
}
return MatchOperand_Success;
@@ -5181,84 +5199,132 @@
}
}
-static unsigned getRealVLDLNOpcode(unsigned Opc) {
+static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) {
switch(Opc) {
default: assert(0 && "unexpected opcode!");
// VLD1LN
case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8:
case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8:
case ARM::VLD1LNdWB_fixed_Asm_U8:
+ Spacing = 1;
return ARM::VLD1LNd8_UPD;
case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16:
case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16:
case ARM::VLD1LNdWB_fixed_Asm_U16:
+ Spacing = 1;
return ARM::VLD1LNd16_UPD;
case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F:
case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32:
case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32:
+ Spacing = 1;
return ARM::VLD1LNd32_UPD;
case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8:
case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8:
case ARM::VLD1LNdWB_register_Asm_U8:
+ Spacing = 1;
return ARM::VLD1LNd8_UPD;
case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16:
case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16:
case ARM::VLD1LNdWB_register_Asm_U16:
+ Spacing = 1;
return ARM::VLD1LNd16_UPD;
case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F:
case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32:
case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32:
+ Spacing = 1;
return ARM::VLD1LNd32_UPD;
case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8:
case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8:
case ARM::VLD1LNdAsm_U8:
+ Spacing = 1;
return ARM::VLD1LNd8;
case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16:
case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
case ARM::VLD1LNdAsm_U16:
+ Spacing = 1;
return ARM::VLD1LNd16;
case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32:
case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32:
+ Spacing = 1;
return ARM::VLD1LNd32;
// VLD2LN
case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
case ARM::VLD2LNdWB_fixed_Asm_U8:
+ Spacing = 1;
return ARM::VLD2LNd8_UPD;
case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16:
case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16:
case ARM::VLD2LNdWB_fixed_Asm_U16:
+ Spacing = 1;
return ARM::VLD2LNd16_UPD;
case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
+ Spacing = 1;
return ARM::VLD2LNd32_UPD;
+ case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
+ case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
+ case ARM::VLD2LNqWB_fixed_Asm_U16:
+ Spacing = 1;
+ return ARM::VLD2LNq16_UPD;
+ case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
+ case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
+ case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32:
+ Spacing = 2;
+ return ARM::VLD2LNq32_UPD;
case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
case ARM::VLD2LNdWB_register_Asm_U8:
+ Spacing = 1;
return ARM::VLD2LNd8_UPD;
case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16:
case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16:
case ARM::VLD2LNdWB_register_Asm_U16:
+ Spacing = 1;
return ARM::VLD2LNd16_UPD;
case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
+ Spacing = 1;
return ARM::VLD2LNd32_UPD;
+ case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
+ case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
+ case ARM::VLD2LNqWB_register_Asm_U16:
+ Spacing = 2;
+ return ARM::VLD2LNq16_UPD;
+ case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
+ case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
+ case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32:
+ Spacing = 2;
+ return ARM::VLD2LNq32_UPD;
case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8:
case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8:
case ARM::VLD2LNdAsm_U8:
+ Spacing = 1;
return ARM::VLD2LNd8;
case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16:
case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
case ARM::VLD2LNdAsm_U16:
+ Spacing = 1;
return ARM::VLD2LNd16;
case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32:
case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32:
+ Spacing = 1;
return ARM::VLD2LNd32;
+ case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
+ case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16:
+ case ARM::VLD2LNqAsm_U16:
+ Spacing = 2;
+ return ARM::VLD2LNq16;
+ case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F:
+ case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32:
+ case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32:
+ Spacing = 2;
+ return ARM::VLD2LNq32;
}
}
@@ -5415,7 +5481,8 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
@@ -5429,26 +5496,34 @@
return true;
}
- case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
- case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
- case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16:
+ case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
+ case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
+ case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16:
case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16:
case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16:
- case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
+ case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
- case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: {
+ case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
+ case ARM::VLD2LNqWB_register_Asm_P16: case ARM::VLD2LNqWB_register_Asm_I16:
+ case ARM::VLD2LNqWB_register_Asm_S16: case ARM::VLD2LNqWB_register_Asm_U16:
+ case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
+ case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
+ case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
TmpInst.addOperand(Inst.getOperand(6));
@@ -5467,7 +5542,8 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
@@ -5481,26 +5557,34 @@
return true;
}
- case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
- case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
- case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16:
+ case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
+ case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
+ case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16:
case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16:
case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16:
- case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
+ case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
- case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: {
+ case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
+ case ARM::VLD2LNqWB_fixed_Asm_P16: case ARM::VLD2LNqWB_fixed_Asm_I16:
+ case ARM::VLD2LNqWB_fixed_Asm_S16: case ARM::VLD2LNqWB_fixed_Asm_U16:
+ case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
+ case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
+ case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
@@ -5517,7 +5601,8 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
@@ -5529,22 +5614,29 @@
return true;
}
- case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8:
- case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16:
+ case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8:
+ case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16:
case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
- case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
+ case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32:
- case ARM::VLD2LNdAsm_U32: {
+ case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
+ case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16:
+ case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32:
+ case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32:
+ case ARM::VLD2LNqAsm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=146983&r1=146982&r2=146983&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Tue Dec 20 13:21:26 2011
@@ -230,8 +230,9 @@
vld2.8 {d16[1], d17[1]}, [r0, :16]
vld2.16 {d16[1], d17[1]}, [r0, :32]
vld2.32 {d16[1], d17[1]}, [r0]
-@ vld2.16 {d17[1], d19[1]}, [r0]
-@ vld2.32 {d17[0], d19[0]}, [r0, :64]
+ vld2.16 {d17[1], d19[1]}, [r0]
+ vld2.32 {d17[0], d19[0]}, [r0, :64]
+ vld2.32 {d17[0], d19[0]}, [r0, :64]!
vld2.8 {d2[4], d3[4]}, [r2], r3
vld2.8 {d2[4], d3[4]}, [r2]!
vld2.8 {d2[4], d3[4]}, [r2]
@@ -239,8 +240,9 @@
@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4]
@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4]
@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4]
-@ FIXME: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4]
-@ FIXME: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4]
+@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4]
+@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4]
+@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]! @ encoding: [0x5d,0x19,0xe0,0xf4]
@ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4]
@ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4]
@ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4]
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