[llvm-commits] [llvm] r146900 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/fcopysign.ll test/CodeGen/Mips/mips64imm.ll

[Akira Hatanaka]

Author: ahatanak
Date: Mon Dec 19 14:21:18 2011
New Revision: 146900

URL: http://llvm.org/viewvc/llvm-project?rev=146900&view=rev
Log:
Add patterns for matching immediates whose lower 16-bit is cleared. These
patterns emit a single LUi instruction instead of a pair of LUi and ORi.


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/test/CodeGen/Mips/fcopysign.ll
    llvm/trunk/test/CodeGen/Mips/mips64imm.ll

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146900&r1=146899&r2=146900&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Dec 19 14:21:18 2011
@@ -225,6 +225,8 @@
           (DADDiu ZERO_64, imm:$in)>;
 def : Pat<(i64 immZExt16:$in),
           (ORi64 ZERO_64, imm:$in)>;
+def : Pat<(i64 immLUiOpnd:$in),
+          (LUi64 (HI16 imm:$in))>;
 
 // 32-bit immediates
 def : Pat<(i64 immSExt32:$imm),

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=146900&r1=146899&r2=146900&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 19 14:21:18 2011
@@ -219,6 +219,12 @@
     return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
 }], LO16>;
 
+// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
+def immLUiOpnd : PatLeaf<(imm), [{
+  int64_t Val = N->getSExtValue();
+  return isInt<32>(Val) && !(Val & 0xffff);
+}]>;
+
 // shamt field must fit in 5 bits.
 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
 
@@ -933,6 +939,8 @@
           (ADDiu ZERO, imm:$in)>;
 def : Pat<(i32 immZExt16:$in),
           (ORi ZERO, imm:$in)>;
+def : Pat<(i32 immLUiOpnd:$in),
+          (LUi (HI16 imm:$in))>;
 
 // Arbitrary immediates
 def : Pat<(i32 imm:$imm),

Modified: llvm/trunk/test/CodeGen/Mips/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcopysign.ll?rev=146900&r1=146899&r2=146900&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcopysign.ll Mon Dec 19 14:21:18 2011
@@ -5,9 +5,8 @@
 define double @func0(double %d0, double %d1) nounwind readnone {
 entry:
 ; MIPS32-EL: func0:
-; MIPS32-EL: lui $[[T1:[0-9]+]], 32768
-; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
 ; MIPS32-EL: mfc1 $[[HI0:[0-9]+]], $f15
+; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768
 ; MIPS32-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
 ; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
 ; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
@@ -18,9 +17,8 @@
 ; MIPS32-EL: mtc1 $[[LO0]], $f0
 ; MIPS32-EL: mtc1 $[[OR]], $f1
 ;
-; MIPS32-EB: lui $[[T1:[0-9]+]], 32768
-; MIPS32-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
 ; MIPS32-EB: mfc1 $[[HI1:[0-9]+]], $f14
+; MIPS32-EB: lui $[[MSK1:[0-9]+]], 32768
 ; MIPS32-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
 ; MIPS32-EB: lui $[[T0:[0-9]+]], 32767
 ; MIPS32-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
@@ -46,9 +44,8 @@
 define float @func1(float %f0, float %f1) nounwind readnone {
 entry:
 ; MIPS32-EL: func1:
-; MIPS32-EL: lui $[[T1:[0-9]+]], 32768
-; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
 ; MIPS32-EL: mfc1 $[[ARG1:[0-9]+]], $f14
+; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768
 ; MIPS32-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
 ; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
 ; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535

Modified: llvm/trunk/test/CodeGen/Mips/mips64imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64imm.ll?rev=146900&r1=146899&r2=146900&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64imm.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64imm.ll Mon Dec 19 14:21:18 2011
@@ -1,5 +1,13 @@
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
 
+define i32 @foo1() nounwind readnone {
+entry:
+; CHECK: foo1
+; CHECK: lui ${{[0-9]+}}, 4660
+; CHECK-NOT: ori
+  ret i32 305397760
+}
+
 define i64 @foo3() nounwind readnone {
 entry:
 ; CHECK: foo3