[llvm-commits] [llvm] r146875 - in /llvm/trunk: docs/ReleaseNotes.html lib/Target/ARM/ARMRegisterInfo.td

[Jakob Stoklund Olesen]

Author: stoklund
Date: Mon Dec 19 10:53:40 2011
New Revision: 146875

URL: http://llvm.org/viewvc/llvm-project?rev=146875&view=rev
Log:
Remove a register class that can just as well be synthesized.

Add the new TableGen register class synthesizer feature to the release
notes.

Modified:
    llvm/trunk/docs/ReleaseNotes.html
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=146875&r1=146874&r2=146875&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Dec 19 10:53:40 2011
@@ -337,7 +337,10 @@
    make it run faster:</p>
 
 <ul>
-  <li>....</li>
+  <li>TableGen can now synthesize register classes that are only needed to
+  represent combinations of constraints from instructions and sub-registers.
+  The synthetic register classes inherit most of their properties form their
+  closest user-defined super-class.</li>
 </ul>
 </div>
 

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=146875&r1=146874&r2=146875&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Dec 19 10:53:40 2011
@@ -326,14 +326,6 @@
   let AltOrderSelect = [{ return 1; }];
 }
 
-// Subset of QQPR that have 32-bit SPR subregs.
-def QQPR_VFP2 : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 4)> {
-  let SubRegClasses = [(SPR      ssub_0, ssub_1, ssub_2, ssub_3),
-                       (DPR_VFP2 dsub_0, dsub_1, dsub_2, dsub_3),
-                       (QPR_VFP2 qsub_0, qsub_1)];
-
-}
-
 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
 // (8 consecutive D registers).
 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (sequence "QQQQ%u", 0, 3)> {