[llvm-commits] [llvm] r146657 - in /llvm/trunk/utils/TableGen: CodeGenRegisters.cpp CodeGenRegisters.h

[Jakob Stoklund Olesen]

After deduping, these are the new classes:

ARM::GPRnopc_and_hGPR
ARM::hGPR_and_rGPR
ARM::hGPR_and_tcGPR
ARM::tGPR_and_tcGPR

X86::GR32_ABCD_and_GR32_NOAX
X86::GR32_AD_and_GR32_NOAX
X86::GR32_NOAX_and_GR32_NOREX
X86::GR32_NOAX_and_GR32_NOREX_NOSP
X86::GR32_NOAX_and_GR32_NOSP
X86::GR32_NOAX_and_GR32_TC
X86::GR64_ABCD_and_GR64_TC
X86::GR64_NOREX_NOSP_and_GR64_TC
X86::GR64_NOREX_and_GR64_TC
X86::GR64_NOSP_and_GR64_TC

/jakob

On Dec 15, 2011, at 8:48 AM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Thu Dec 15 10:48:55 2011
> New Revision: 146657
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=146657&view=rev
> Log:
> Synthesize missing register class intersections.
> 
> The function TRI::getCommonSubClass(A, B) returns the largest common
> sub-class of the register classes A and B.  This patch teaches TableGen
> to synthesize sub-classes such that the answer is always maximal.
> 
> In other words, every register that is in both A and B will also be
> present in getCommonSubClass(A, B).
> 
> This introduces these synthetic register classes:
> 
> ARM:
>    GPRnopc_and_hGPR
>    GPRnopc_and_hGPR
>    hGPR_and_rGPR
>    GPRnopc_and_hGPR
>    GPRnopc_and_hGPR
>    hGPR_and_rGPR
>    tGPR_and_tcGPR
>    hGPR_and_tcGPR
> 
> X86:
>    GR32_NOAX_and_GR32_NOSP
>    GR32_NOAX_and_GR32_NOREX
>    GR64_NOSP_and_GR64_TC
>    GR64_NOSP_and_GR64_TC
>    GR64_NOREX_and_GR64_TC
>    GR32_NOAX_and_GR32_NOSP
>    GR32_NOAX_and_GR32_NOREX
>    GR32_NOAX_and_GR32_NOREX_NOSP
>    GR64_NOSP_and_GR64_TC
>    GR64_NOREX_and_GR64_TC
>    GR64_NOREX_NOSP_and_GR64_TC
>    GR32_NOAX_and_GR32_NOSP
>    GR32_NOAX_and_GR32_NOREX
>    GR32_NOAX_and_GR32_NOREX_NOSP
>    GR32_ABCD_and_GR32_NOAX
>    GR32_NOAX_and_GR32_NOSP
>    GR32_NOAX_and_GR32_NOREX
>    GR32_NOAX_and_GR32_NOREX_NOSP
>    GR32_ABCD_and_GR32_NOAX
>    GR32_NOAX_and_GR32_TC
>    GR32_NOAX_and_GR32_NOSP
>    GR64_NOSP_and_GR64_TC
>    GR32_NOAX_and_GR32_NOREX
>    GR32_NOAX_and_GR32_NOREX_NOSP
>    GR64_NOREX_and_GR64_TC
>    GR64_NOREX_NOSP_and_GR64_TC
>    GR32_ABCD_and_GR32_NOAX
>    GR64_ABCD_and_GR64_TC
>    GR32_NOAX_and_GR32_TC
>    GR32_AD_and_GR32_NOAX
> 
> Other targets are unaffected.
> 
> Modified:
>    llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
>    llvm/trunk/utils/TableGen/CodeGenRegisters.h
> 
> Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=146657&r1=146656&r2=146657&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
> +++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Thu Dec 15 10:48:55 2011
> @@ -756,6 +756,43 @@
>   computeComposites();
> }
> 
> +//
> +// Synthesize missing register class intersections.
> +//
> +// Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
> +// returns a maximal register class for all X.
> +//
> +void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
> +  for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) {
> +    CodeGenRegisterClass *RC1 = RC;
> +    CodeGenRegisterClass *RC2 = RegClasses[rci];
> +    if (RC1 == RC2)
> +      continue;
> +
> +    // Compute the set intersection of RC1 and RC2.
> +    const CodeGenRegister::Set &Memb1 = RC1->getMembers();
> +    const CodeGenRegister::Set &Memb2 = RC2->getMembers();
> +    CodeGenRegister::Set Intersection;
> +    std::set_intersection(Memb1.begin(), Memb1.end(),
> +                          Memb2.begin(), Memb2.end(),
> +                          std::inserter(Intersection, Intersection.begin()));
> +
> +    // Skip disjoint class pairs.
> +    if (Intersection.empty())
> +      continue;
> +
> +    // If RC1 and RC2 have different spill sizes or alignments, use the
> +    // larger size for sub-classing.  If they are equal, prefer RC1.
> +    if (RC2->SpillSize > RC1->SpillSize ||
> +        (RC2->SpillSize == RC1->SpillSize &&
> +         RC2->SpillAlignment > RC1->SpillAlignment))
> +      std::swap(RC1, RC2);
> +
> +    getOrCreateSubClass(RC1, &Intersection,
> +                        RC1->getName() + "_and_" + RC2->getName());
> +  }
> +}
> +
> // Infer missing register classes.
> //
> // For every register class RC, make sure that the set of registers in RC with
> @@ -801,6 +838,9 @@
>                             RC.getName() + "_with_" + I->first->getName());
>       RC.setSubClassWithSubReg(SubIdx, SubRC);
>     }
> +
> +    // Synthesize answers for getCommonSubClass().
> +    inferCommonSubClass(&RC);
>   }
> }
> 
> 
> Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=146657&r1=146656&r2=146657&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original)
> +++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Thu Dec 15 10:48:55 2011
> @@ -244,6 +244,7 @@
> 
>     // Infer missing register classes.
>     void computeInferredRegisterClasses();
> +    void inferCommonSubClass(CodeGenRegisterClass *RC);
> 
>     // Composite SubRegIndex instances.
>     // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
> 
> 
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