[llvm-commits] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading: Obvious fixes.

[Stepan Dyatkovskiy]

Hi all. Please find some obvious fixes for <n x i1> .. <n x i7> vectors.
I fixed 'load' expansion, since there was improper stride calculation.
I also fixed some assertion for trunc store. Assertion dropped for trunc 
stores with non simple MemoryVT. MemoryVT <n x i1> will never became 
simple in ToT. I inserted the store expansion in this case.

-Stepan.
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