[llvm-commits] [llvm] r146547 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/ScheduleDAGInstrs.cpp
Evan Cheng
evan.cheng at apple.com
Tue Dec 13 18:28:53 PST 2011
Author: evancheng
Date: Tue Dec 13 20:28:53 2011
New Revision: 146547
URL: http://llvm.org/viewvc/llvm-project?rev=146547&view=rev
Log:
Allow target to specify register output dependency. Still default to one.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=146547&r1=146546&r2=146547&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Dec 13 20:28:53 2011
@@ -648,6 +648,16 @@
SDNode *DefNode, unsigned DefIdx,
SDNode *UseNode, unsigned UseIdx) const;
+ /// getOutputLatency - Compute and return the output dependency latency of a
+ /// a given pair of defs which both target the same register. This is usually
+ /// one.
+ virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
+ const MachineInstr *DefMI1,
+ const MachineInstr *DefMI2,
+ unsigned Reg) const {
+ return 1;
+ }
+
/// getInstrLatency - Compute the instruction latency of a given instruction.
/// If the instruction has higher cost when predicated, it's returned via
/// PredCost.
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=146547&r1=146546&r2=146547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Dec 13 20:28:53 2011
@@ -278,7 +278,13 @@
if (DefSU != SU &&
(Kind != SDep::Output || !MO.isDead() ||
!DefSU->getInstr()->registerDefIsDead(Reg))) {
- DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
+ if (Kind == SDep::Anti)
+ DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg));
+ else {
+ unsigned AOLat = TII->getOutputLatency(InstrItins, MI,
+ DefSU->getInstr(), Reg);
+ DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg));
+ }
}
}
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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