[llvm-commits] PATCH: Enable direct selection of bsf and bsr instructions for cttz and ctlz with zero-undef behavior

[Chandler Carruth]

This just enables the necessary patterns for x86. I really know nothing
about the tablegen-backed patterns, so please review and be gentle. =]

There is still quite a bit of work to be done on the zero-undef front. We
need to teach the entire middle end about this behavior and have it
transform both to and from the zero-undef variants based on conditions and
known bits of the operand. I've updated the test to demonstrate that no
more cmov instructions are generated for the common case, but we still
generate them when required by the instruction semantics unless there are
trivially bits set in the operand.

This also doesn't teach the x86 backend to prefer bsf and bsr when they are
sufficient even though lzcnt and tzcnt are available. That behavior would
be beneficial as bsf and bsr encode more compactly. If someone can shed
light on how to do this, that would really help. I'm completely out of my
depth in the actual target pattern magic of TableGen. =]
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