[llvm-commits] [llvm] r146322 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
Stepan Dyatkovskiy
stpworld at narod.ru
Sun Dec 11 05:53:10 PST 2011
Thanks! It works!
Benjamin Kramer wrote:
>
> On 11.12.2011, at 14:23, Stepan Dyatkovskiy wrote:
>
>> Thanks. Chad. I tried to pick up proper "CHECKs" for this platform but
>> it is still fails :-( I'll ask for somebody to get stdout that produced
>> by llc with this test. Or may be it is possible to get ssh access to
>> llvm-ppc-darwin?
>
> It's probably reproducible if you pass a darwin triple to llc, e.g. "-mtriple=armv7-apple-darwin11"
>
> - Ben
>
>>
>> -Stepan.
>>
>> Chad Rosier wrote:
>>> Reverted in r146328. Please recommit once you've made the necessary fixes.
>>>
>>> Chad
>>>
>>> On Dec 10, 2011, at 10:37 AM, Chad Rosier wrote:
>>>
>>>> Hi Stepan,
>>>> This commit is causing our internal buildbots to fail. The included test is failing with the following error(s):
>>>>
>>>> ********************
>>>> FAIL: LLVM :: CodeGen/ARM/2011-11-29-128bitArithmetics.ll (4566 of 9666)
>>>> ******************** TEST 'LLVM :: CodeGen/ARM/2011-11-29-128bitArithmetics.ll' FAILED ********************
>>>> Script:
>>>> --
>>>> /Users/mcrosier/llvm-clean/Release+Asserts/Release+Asserts/bin/llc< /Users/mcrosier/llvm-clean/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll -march=arm -mcpu=cortex-a9 | /Users/mcrosier/llvm-clean/Release+Asserts/Release+Asserts/bin/FileCheck /Users/mcrosier/llvm-clean/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>>>> --
>>>> Exit Code: 1
>>>> Command Output (stderr):
>>>> --
>>>> /Users/mcrosier/llvm-clean/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll:33:15: error: CHECK-NEXT: is not on the line after the previous match
>>>> ; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>> ^
>>>> <stdin>:33:2: note: 'next' match was here
>>>> movt r1, :upper16:(_A-(LPC1_0+8))
>>>> ^
>>>> <stdin>:31:35: note: previous match was here
>>>> movw r1, :lower16:(_A-(LPC1_0+8))
>>>> ^
>>>> --
>>>>
>>>> Please fix or revert.
>>>>
>>>> Thanks,
>>>> Chad
>>>>
>>>> On Dec 10, 2011, at 12:42 AM, Stepan Dyatkovskiy wrote:
>>>>
>>>>> Author: dyatkovskiy
>>>>> Date: Sat Dec 10 02:42:24 2011
>>>>> New Revision: 146322
>>>>>
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=146322&view=rev
>>>>> Log:
>>>>> Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
>>>>>
>>>>> Added:
>>>>> llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>>>>> Modified:
>>>>> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>>>>
>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=146322&r1=146321&r2=146322&view=diff
>>>>> ==============================================================================
>>>>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>>>>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sat Dec 10 02:42:24 2011
>>>>> @@ -468,13 +468,23 @@
>>>>>
>>>>> // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
>>>>> // neither Neon nor VFP support any arithmetic operations on it.
>>>>> + // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
>>>>> + // supported for v4f32.
>>>>> setOperationAction(ISD::FADD, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
>>>>> + // FIXME: Code duplication: FDIV and FREM are expanded always, see
>>>>> + // ARMTargetLowering::addTypeForNEON method for details.
>>>>> setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FREM, MVT::v2f64, Expand);
>>>>> + // FIXME: Create unittest.
>>>>> + // In another words, find a way when "copysign" appears in DAG with vector
>>>>> + // operands.
>>>>> setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
>>>>> + // FIXME: Code duplication: SETCC has custom operation action, see
>>>>> + // ARMTargetLowering::addTypeForNEON method for details.
>>>>> setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
>>>>> + // FIXME: Create unittest for FNEG and for FABS.
>>>>> setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FABS, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
>>>>> @@ -487,11 +497,23 @@
>>>>> setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
>>>>> + // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
>>>>> setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
>>>>> setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
>>>>> +
>>>>> + setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
>>>>> + setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
>>>>>
>>>>> // Neon does not support some operations on v1i64 and v2i64 types.
>>>>> setOperationAction(ISD::MUL, MVT::v1i64, Expand);
>>>>>
>>>>> Added: llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll?rev=146322&view=auto
>>>>> ==============================================================================
>>>>> --- llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll (added)
>>>>> +++ llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll Sat Dec 10 02:42:24 2011
>>>>> @@ -0,0 +1,302 @@
>>>>> +; RUN: llc< %s -march=arm -mcpu=cortex-a9 | FileCheck %s
>>>>> +
>>>>> + at A = global<4 x float> <float 0., float 1., float 2., float 3.>
>>>>> +
>>>>> +define void @test_sqrt(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_sqrt:
>>>>> +
>>>>> +; CHECK: movw r1, :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt r1, :upper16:{{.*}}
>>>>> +; CHECK: vldmia r1, {[[short0:s[0-9]+]], [[short1:s[0-9]+]], [[short2:s[0-9]+]], [[short3:s[0-9]+]]}
>>>>> +; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short3]]
>>>>> +; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short2]]
>>>>> +; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short1]]
>>>>> +; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short0]]
>>>>> +; CHECK-NEXT: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
>>>>> +
>>>>> +
>>>>> +define void @test_cos(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_cos:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK: vldmia [[reg0]], {{.*}}
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl cosf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl cosf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl cosf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl cosf
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.cos.v4f32(<4 x float> %0)
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
>>>>> +
>>>>> +define void @test_exp(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_exp:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK: vldmia [[reg0]], {{.*}}
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl expf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl expf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl expf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl expf
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.exp.v4f32(<4 x float> %0)
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
>>>>> +
>>>>> +define void @test_exp2(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_exp2:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK: vldmia [[reg0]], {{.*}}
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl exp2f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl exp2f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl exp2f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl exp2f
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.exp2.v4f32(<4 x float> %0)
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
>>>>> +
>>>>> +define void @test_log10(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_log10:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK: vldmia [[reg0]], {{.*}}
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl log10f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl log10f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl log10f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl log10f
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.log10.v4f32(<4 x float> %0)
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
>>>>> +
>>>>> +define void @test_log(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_log:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK: vldmia [[reg0]], {{.*}}
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl logf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl logf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl logf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl logf
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.log.v4f32(<4 x float> %0)
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
>>>>> +
>>>>> +define void @test_log2(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_log2:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK: vldmia [[reg0]], {{.*}}
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl log2f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl log2f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl log2f
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl log2f
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.log2.v4f32(<4 x float> %0)
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
>>>>> +
>>>>> +
>>>>> +define void @test_pow(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_pow:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK: vldmia [[reg0]], {{.*}}
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl powf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl powf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl powf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl powf
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> +
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.pow.v4f32(<4 x float> %0,<4 x float> <float 2., float 2., float 2., float 2.>)
>>>>> +
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> +
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.pow.v4f32(<4 x float>,<4 x float>) nounwind readonly
>>>>> +
>>>>> +define void @test_powi(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_powi:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK-NEXT: vldmia [[reg0]], {{.*}}
>>>>> +; CHECK: vmul.f32 {{.*}}
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> +
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
>>>>> +
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> +
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
>>>>> +
>>>>> +define void @test_sin(<4 x float>* %X) nounwind {
>>>>> +
>>>>> +; CHECK: test_sin:
>>>>> +
>>>>> +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
>>>>> +; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
>>>>> +; CHECK: vldmia [[reg0]], {{.*}}
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl sinf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl sinf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl sinf
>>>>> +
>>>>> +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
>>>>> +; CHECK: bl sinf
>>>>> +
>>>>> +; CHECK: vstmia {{.*}}
>>>>> +
>>>>> +L.entry:
>>>>> + %0 = load<4 x float>* @A, align 16
>>>>> + %1 = call<4 x float> @llvm.sin.v4f32(<4 x float> %0)
>>>>> + store<4 x float> %1,<4 x float>* %X, align 16
>>>>> + ret void
>>>>> +}
>>>>> +
>>>>> +declare<4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
>>>>> +
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
More information about the llvm-commits
mailing list