[llvm-commits] [llvm] r146318 - in /llvm/trunk: lib/Target/PowerPC/PPCRegisterInfo.cpp test/CodeGen/PowerPC/2010-02-12-saveCR.ll test/CodeGen/PowerPC/ppc32-vaarg.ll
Hal Finkel
hfinkel at anl.gov
Fri Dec 9 20:50:53 PST 2011
Author: hfinkel
Date: Fri Dec 9 22:50:53 2011
New Revision: 146318
URL: http://llvm.org/viewvc/llvm-project?rev=146318&view=rev
Log:
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=146318&r1=146317&r2=146318&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Dec 9 22:50:53 2011
@@ -464,12 +464,16 @@
MachineBasicBlock &MBB = *MI.getParent();
DebugLoc dl = MI.getDebugLoc();
- const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
- const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
- const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
- unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
- unsigned SrcReg = MI.getOperand(0).getReg();
+ // FIXME: Once LLVM supports creating virtual registers here, or the register
+ // scavenger can return multiple registers, stop using reserved registers
+ // here.
+ (void) SPAdj;
+ (void) RS;
+
bool LP64 = Subtarget.isPPC64();
+ unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
+ (LP64 ? PPC::X0 : PPC::R0);
+ unsigned SrcReg = MI.getOperand(0).getReg();
// We need to store the CR in the low 4-bits of the saved value. First, issue
// an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
@@ -503,14 +507,18 @@
MachineBasicBlock &MBB = *MI.getParent();
DebugLoc dl = MI.getDebugLoc();
- const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
- const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
- const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
- unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
+ // FIXME: Once LLVM supports creating virtual registers here, or the register
+ // scavenger can return multiple registers, stop using reserved registers
+ // here.
+ (void) SPAdj;
+ (void) RS;
+
+ bool LP64 = Subtarget.isPPC64();
+ unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
+ (LP64 ? PPC::X0 : PPC::R0);
unsigned DestReg = MI.getOperand(0).getReg();
assert(MI.definesRegister(DestReg) &&
"RESTORE_CR does not define its destination");
- bool LP64 = Subtarget.isPPC64();
addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
Reg), FrameIndex);
Modified: llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll?rev=146318&r1=146317&r2=146318&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll Fri Dec 9 22:50:53 2011
@@ -6,11 +6,11 @@
define void @foo() nounwind {
entry:
-;CHECK: lis r4, 1
-;CHECK: ori r4, r4, 34524
-;CHECK: mfcr r3
-;CHECK: rlwinm r3, r3, 8, 0, 31
-;CHECK: stwx r3, r1, r4
+;CHECK: lis r3, 1
+;CHECK: ori r3, r3, 34524
+;CHECK: mfcr r2
+;CHECK: rlwinm r2, r2, 8, 0, 31
+;CHECK: stwx r2, r1, r3
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
@@ -21,9 +21,9 @@
return: ; preds = %entry
;CHECK: lis r3, 1
;CHECK: ori r3, r3, 34524
-;CHECK: lwzx r3, r1, r3
-;CHECK: rlwinm r3, r3, 24, 0, 31
-;CHECK: mtcrf 32, r3
+;CHECK: lwzx r2, r1, r3
+;CHECK: rlwinm r2, r2, 24, 0, 31
+;CHECK: mtcrf 32, r2
ret void
}
Modified: llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll?rev=146318&r1=146317&r2=146318&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Fri Dec 9 22:50:53 2011
@@ -37,8 +37,8 @@
; CHECK-NEXT: stw 3, -24(1)
; CHECK-NEXT: stw 8, -28(1)
; CHECK-NEXT: stw 6, -32(1)
-; CHECK-NEXT: mfcr 3 # cr0
-; CHECK-NEXT: stw 3, -36(1)
+; CHECK-NEXT: mfcr 0 # cr0
+; CHECK-NEXT: stw 0, -36(1)
; CHECK-NEXT: blt 0, .LBB0_4
; CHECK-NEXT: # BB#3: # %entry
; CHECK-NEXT: lwz 3, -20(1)
@@ -52,8 +52,8 @@
; CHECK-NEXT: slwi 5, 3, 2
; CHECK-NEXT: lwz 6, -16(1)
; CHECK-NEXT: add 5, 6, 5
-; CHECK-NEXT: lwz 3, -36(1)
-; CHECK-NEXT: mtcrf 128, 3
+; CHECK-NEXT: lwz 0, -36(1)
+; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 5, -40(1)
; CHECK-NEXT: blt 0, .LBB0_6
; CHECK-NEXT: # BB#5: # %entry
@@ -82,8 +82,8 @@
; CHECK-NEXT: stw 4, -52(1)
; CHECK-NEXT: stw 6, -56(1)
; CHECK-NEXT: stw 8, -60(1)
-; CHECK-NEXT: mfcr 3 # cr0
-; CHECK-NEXT: stw 3, -64(1)
+; CHECK-NEXT: mfcr 0 # cr0
+; CHECK-NEXT: stw 0, -64(1)
; CHECK-NEXT: blt 0, .LBB0_8
; CHECK-NEXT: # BB#7: # %entry
; CHECK-NEXT: lwz 3, -48(1)
@@ -97,8 +97,8 @@
; CHECK-NEXT: lwz 6, -56(1)
; CHECK-NEXT: add 5, 6, 5
; CHECK-NEXT: addi 5, 5, 32
-; CHECK-NEXT: lwz 3, -64(1)
-; CHECK-NEXT: mtcrf 128, 3
+; CHECK-NEXT: lwz 0, -64(1)
+; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 5, -68(1)
; CHECK-NEXT: blt 0, .LBB0_10
; CHECK-NEXT: # BB#9: # %entry
@@ -122,8 +122,8 @@
; CHECK-NEXT: mr 8, 5
; CHECK-NEXT: stw 4, -72(1)
; CHECK-NEXT: stw 6, -76(1)
-; CHECK-NEXT: mfcr 3 # cr0
-; CHECK-NEXT: stw 3, -80(1)
+; CHECK-NEXT: mfcr 0 # cr0
+; CHECK-NEXT: stw 0, -80(1)
; CHECK-NEXT: stw 5, -84(1)
; CHECK-NEXT: stw 8, -88(1)
; CHECK-NEXT: stw 7, -92(1)
@@ -139,8 +139,8 @@
; CHECK-NEXT: slwi 5, 3, 2
; CHECK-NEXT: lwz 6, -76(1)
; CHECK-NEXT: add 5, 6, 5
-; CHECK-NEXT: lwz 3, -80(1)
-; CHECK-NEXT: mtcrf 128, 3
+; CHECK-NEXT: lwz 0, -80(1)
+; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 5, -96(1)
; CHECK-NEXT: blt 0, .LBB0_14
; CHECK-NEXT: # BB#13: # %entry
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