[llvm-commits] [llvm] r146086 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/cmov.ll
Akira Hatanaka
ahatanaka at mips.com
Wed Dec 7 14:11:44 PST 2011
Author: ahatanak
Date: Wed Dec 7 16:11:43 2011
New Revision: 146086
URL: http://llvm.org/viewvc/llvm-project?rev=146086&view=rev
Log:
64-bit WrapperPICPat patterns.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/test/CodeGen/Mips/cmov.ll
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146086&r1=146085&r2=146086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Dec 7 16:11:43 2011
@@ -273,6 +273,12 @@
def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
(DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
+def : WrapperPICPat<tglobaladdr, DADDiu, GP_64>;
+def : WrapperPICPat<tconstpool, DADDiu, GP_64>;
+def : WrapperPICPat<texternalsym, DADDiu, GP_64>;
+def : WrapperPICPat<tblockaddress, DADDiu, GP_64>;
+def : WrapperPICPat<tjumptable, DADDiu, GP_64>;
+
defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
ZERO_64>;
Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=146086&r1=146085&r2=146086&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cmov.ll Wed Dec 7 16:11:43 2011
@@ -1,11 +1,14 @@
-; RUN: llc -march=mips < %s | FileCheck %s
-; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32
+; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s -check-prefix=O32
+; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
-; CHECK: lw ${{[0-9]+}}, %got(i3)($gp)
-; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1)
+; O32: lw ${{[0-9]+}}, %got(i3)($gp)
+; O32: addiu ${{[0-9]+}}, $gp, %got(i1)
+; N64: ld ${{[0-9]+}}, %got_disp(i3)($gp)
+; N64: daddiu ${{[0-9]+}}, $gp, %got_disp(i1)
define i32* @cmov1(i32 %s) nounwind readonly {
entry:
%tobool = icmp ne i32 %s, 0
@@ -17,10 +20,14 @@
@c = global i32 1, align 4
@d = global i32 0, align 4
-; CHECK: cmov2:
-; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d)
-; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
-; CHECK: movn $[[R1]], $[[R0]], ${{[0-9]+}}
+; O32: cmov2:
+; O32: addiu $[[R1:[0-9]+]], $gp, %got(d)
+; O32: addiu $[[R0:[0-9]+]], $gp, %got(c)
+; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
+; N64: cmov2:
+; N64: daddiu $[[R1:[0-9]+]], $gp, %got_disp(d)
+; N64: daddiu $[[R0:[0-9]+]], $gp, %got_disp(c)
+; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}}
define i32 @cmov2(i32 %s) nounwind readonly {
entry:
%tobool = icmp ne i32 %s, 0
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