[llvm-commits] [llvm] r145718 - in /llvm/trunk/lib/Target/ARM: ARMInstrNEON.td AsmParser/ARMAsmParser.cpp
Jim Grosbach
grosbach at apple.com
Fri Dec 2 14:34:51 PST 2011
Author: grosbach
Date: Fri Dec 2 16:34:51 2011
New Revision: 145718
URL: http://llvm.org/viewvc/llvm-project?rev=145718&view=rev
Log:
ARM VST1 single lane assembly parsing.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145718&r1=145717&r2=145718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Dec 2 16:34:51 2011
@@ -5620,3 +5620,32 @@
NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
+
+
+// VST1 single-lane pseudo-instructions. These need special handling for
+// the lane index that an InstAlias can't handle, so we use these instead.
+defm VST1LNdAsm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST1LNdAsm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST1LNdAsm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+
+defm VST1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr!",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr!",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr!",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST1LNdWB_register_Asm :
+ NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
+defm VST1LNdWB_register_Asm :
+ NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
+defm VST1LNdWB_register_Asm :
+ NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=145718&r1=145717&r2=145718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Dec 2 16:34:51 2011
@@ -4751,7 +4751,61 @@
return false;
}
-static unsigned getRealVLDNOpcode(unsigned Opc) {
+static unsigned getRealVSTLNOpcode(unsigned Opc) {
+ switch(Opc) {
+ default: assert(0 && "unexpected opcode!");
+ case ARM::VST1LNdWB_fixed_Asm_8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_P8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_I8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_S8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_U8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_P16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_I16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_S16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_U16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_F: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_F32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_I32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_S32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_fixed_Asm_U32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_register_Asm_8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_register_Asm_P8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_register_Asm_I8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_register_Asm_S8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_register_Asm_U8: return ARM::VST1LNd8_UPD;
+ case ARM::VST1LNdWB_register_Asm_16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_register_Asm_P16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_register_Asm_I16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_register_Asm_S16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_register_Asm_U16: return ARM::VST1LNd16_UPD;
+ case ARM::VST1LNdWB_register_Asm_32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_register_Asm_F: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_register_Asm_F32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_register_Asm_I32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_register_Asm_S32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdWB_register_Asm_U32: return ARM::VST1LNd32_UPD;
+ case ARM::VST1LNdAsm_8: return ARM::VST1LNd8;
+ case ARM::VST1LNdAsm_P8: return ARM::VST1LNd8;
+ case ARM::VST1LNdAsm_I8: return ARM::VST1LNd8;
+ case ARM::VST1LNdAsm_S8: return ARM::VST1LNd8;
+ case ARM::VST1LNdAsm_U8: return ARM::VST1LNd8;
+ case ARM::VST1LNdAsm_16: return ARM::VST1LNd16;
+ case ARM::VST1LNdAsm_P16: return ARM::VST1LNd16;
+ case ARM::VST1LNdAsm_I16: return ARM::VST1LNd16;
+ case ARM::VST1LNdAsm_S16: return ARM::VST1LNd16;
+ case ARM::VST1LNdAsm_U16: return ARM::VST1LNd16;
+ case ARM::VST1LNdAsm_32: return ARM::VST1LNd32;
+ case ARM::VST1LNdAsm_F: return ARM::VST1LNd32;
+ case ARM::VST1LNdAsm_F32: return ARM::VST1LNd32;
+ case ARM::VST1LNdAsm_I32: return ARM::VST1LNd32;
+ case ARM::VST1LNdAsm_S32: return ARM::VST1LNd32;
+ case ARM::VST1LNdAsm_U32: return ARM::VST1LNd32;
+ }
+}
+
+static unsigned getRealVLDLNOpcode(unsigned Opc) {
switch(Opc) {
default: assert(0 && "unexpected opcode!");
case ARM::VLD1LNdWB_fixed_Asm_8: return ARM::VLD1LNd8_UPD;
@@ -4809,6 +4863,98 @@
processInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
switch (Inst.getOpcode()) {
+ // Handle NEON VST1 complex aliases.
+ case ARM::VST1LNdWB_register_Asm_8:
+ case ARM::VST1LNdWB_register_Asm_P8:
+ case ARM::VST1LNdWB_register_Asm_I8:
+ case ARM::VST1LNdWB_register_Asm_S8:
+ case ARM::VST1LNdWB_register_Asm_U8:
+ case ARM::VST1LNdWB_register_Asm_16:
+ case ARM::VST1LNdWB_register_Asm_P16:
+ case ARM::VST1LNdWB_register_Asm_I16:
+ case ARM::VST1LNdWB_register_Asm_S16:
+ case ARM::VST1LNdWB_register_Asm_U16:
+ case ARM::VST1LNdWB_register_Asm_32:
+ case ARM::VST1LNdWB_register_Asm_F:
+ case ARM::VST1LNdWB_register_Asm_F32:
+ case ARM::VST1LNdWB_register_Asm_I32:
+ case ARM::VST1LNdWB_register_Asm_S32:
+ case ARM::VST1LNdWB_register_Asm_U32: {
+ MCInst TmpInst;
+ // Shuffle the operands around so the lane index operand is in the
+ // right place.
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn
+ TmpInst.addOperand(Inst.getOperand(3)); // alignment
+ TmpInst.addOperand(Inst.getOperand(4)); // Rm
+ TmpInst.addOperand(Inst.getOperand(0)); // Vd
+ TmpInst.addOperand(Inst.getOperand(1)); // lane
+ TmpInst.addOperand(Inst.getOperand(5)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(6));
+ Inst = TmpInst;
+ return true;
+ }
+ case ARM::VST1LNdWB_fixed_Asm_8:
+ case ARM::VST1LNdWB_fixed_Asm_P8:
+ case ARM::VST1LNdWB_fixed_Asm_I8:
+ case ARM::VST1LNdWB_fixed_Asm_S8:
+ case ARM::VST1LNdWB_fixed_Asm_U8:
+ case ARM::VST1LNdWB_fixed_Asm_16:
+ case ARM::VST1LNdWB_fixed_Asm_P16:
+ case ARM::VST1LNdWB_fixed_Asm_I16:
+ case ARM::VST1LNdWB_fixed_Asm_S16:
+ case ARM::VST1LNdWB_fixed_Asm_U16:
+ case ARM::VST1LNdWB_fixed_Asm_32:
+ case ARM::VST1LNdWB_fixed_Asm_F:
+ case ARM::VST1LNdWB_fixed_Asm_F32:
+ case ARM::VST1LNdWB_fixed_Asm_I32:
+ case ARM::VST1LNdWB_fixed_Asm_S32:
+ case ARM::VST1LNdWB_fixed_Asm_U32: {
+ MCInst TmpInst;
+ // Shuffle the operands around so the lane index operand is in the
+ // right place.
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn
+ TmpInst.addOperand(Inst.getOperand(3)); // alignment
+ TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(Inst.getOperand(0)); // Vd
+ TmpInst.addOperand(Inst.getOperand(1)); // lane
+ TmpInst.addOperand(Inst.getOperand(4)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(5));
+ Inst = TmpInst;
+ return true;
+ }
+ case ARM::VST1LNdAsm_8:
+ case ARM::VST1LNdAsm_P8:
+ case ARM::VST1LNdAsm_I8:
+ case ARM::VST1LNdAsm_S8:
+ case ARM::VST1LNdAsm_U8:
+ case ARM::VST1LNdAsm_16:
+ case ARM::VST1LNdAsm_P16:
+ case ARM::VST1LNdAsm_I16:
+ case ARM::VST1LNdAsm_S16:
+ case ARM::VST1LNdAsm_U16:
+ case ARM::VST1LNdAsm_32:
+ case ARM::VST1LNdAsm_F:
+ case ARM::VST1LNdAsm_F32:
+ case ARM::VST1LNdAsm_I32:
+ case ARM::VST1LNdAsm_S32:
+ case ARM::VST1LNdAsm_U32: {
+ MCInst TmpInst;
+ // Shuffle the operands around so the lane index operand is in the
+ // right place.
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn
+ TmpInst.addOperand(Inst.getOperand(3)); // alignment
+ TmpInst.addOperand(Inst.getOperand(0)); // Vd
+ TmpInst.addOperand(Inst.getOperand(1)); // lane
+ TmpInst.addOperand(Inst.getOperand(4)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(5));
+ Inst = TmpInst;
+ return true;
+ }
// Handle NEON VLD1 complex aliases.
case ARM::VLD1LNdWB_register_Asm_8:
case ARM::VLD1LNdWB_register_Asm_P8:
@@ -4829,7 +4975,7 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
@@ -4861,7 +5007,7 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
@@ -4893,7 +5039,7 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
+ TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
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