[llvm-commits] [llvm] r145712 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td AsmParser/ARMAsmParser.cpp
Jim Grosbach
grosbach at apple.com
Fri Dec 2 14:01:52 PST 2011
Author: grosbach
Date: Fri Dec 2 16:01:52 2011
New Revision: 145712
URL: http://llvm.org/viewvc/llvm-project?rev=145712&view=rev
Log:
ARM VLD1 single lane assembly parsing.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=145712&r1=145711&r2=145712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Dec 2 16:01:52 2011
@@ -1994,7 +1994,7 @@
// VFP/NEON Instruction aliases for type suffices.
class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
- InstAlias<!strconcat(opc, dt, asm), Result>;
+ InstAlias<!strconcat(opc, dt, "\t", asm), Result>;
multiclass VFPDT8ReqInstAlias<string opc, string asm, dag Result> {
def I8 : VFPDataTypeInstAlias<opc, ".i8", asm, Result>;
def S8 : VFPDataTypeInstAlias<opc, ".s8", asm, Result>;
@@ -2071,7 +2071,7 @@
// above, as we care about the ultimate instruction enum names generated, unlike
// for instalias defs.
class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
- AsmPseudoInst<!strconcat(opc, dt, asm), iops>, Requires<[HasNEON]>;
+ AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
multiclass NEONDT8ReqAsmPseudoInst<string opc, string asm, dag iops> {
def I8 : NEONDataTypeAsmPseudoInst<opc, ".i8", asm, iops>;
def S8 : NEONDataTypeAsmPseudoInst<opc, ".s8", asm, iops>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145712&r1=145711&r2=145712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Dec 2 16:01:52 2011
@@ -5593,11 +5593,30 @@
defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
(VTRNq32 QPR:$Qd, QPR:$Qm, pred:$p)>;
-// FIXME: Proof of concept pseudos. We want to parameterize these for all
-// the suffices we have to support.
+// VLD1 single-lane pseudo-instructions. These need special handling for
+// the lane index that an InstAlias can't handle, so we use these instead.
defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VLD1LNdAsm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VLD1LNdAsm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+
+defm VLD1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr!",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr!",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr!",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD1LNdWB_register_Asm :
+ NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
+defm VLD1LNdWB_register_Asm :
+ NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
+defm VLD1LNdWB_register_Asm :
+ NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
+ (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=145712&r1=145711&r2=145712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Dec 2 16:01:52 2011
@@ -4754,16 +4754,48 @@
static unsigned getRealVLDNOpcode(unsigned Opc) {
switch(Opc) {
default: assert(0 && "unexpected opcode!");
+ case ARM::VLD1LNdWB_fixed_Asm_8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_P8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_I8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_S8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_U8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_P16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_I16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_S16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_U16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_F: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_F32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_I32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_S32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_fixed_Asm_U32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_register_Asm_8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_register_Asm_P8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_register_Asm_I8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_register_Asm_S8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_register_Asm_U8: return ARM::VLD1LNd8_UPD;
+ case ARM::VLD1LNdWB_register_Asm_16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_register_Asm_P16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_register_Asm_I16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_register_Asm_S16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_register_Asm_U16: return ARM::VLD1LNd16_UPD;
+ case ARM::VLD1LNdWB_register_Asm_32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_register_Asm_F: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_register_Asm_F32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_register_Asm_I32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_register_Asm_S32: return ARM::VLD1LNd32_UPD;
+ case ARM::VLD1LNdWB_register_Asm_U32: return ARM::VLD1LNd32_UPD;
case ARM::VLD1LNdAsm_8: return ARM::VLD1LNd8;
case ARM::VLD1LNdAsm_P8: return ARM::VLD1LNd8;
case ARM::VLD1LNdAsm_I8: return ARM::VLD1LNd8;
case ARM::VLD1LNdAsm_S8: return ARM::VLD1LNd8;
case ARM::VLD1LNdAsm_U8: return ARM::VLD1LNd8;
- case ARM::VLD1LNdAsm_16: return ARM::VLD1LNd16;
- case ARM::VLD1LNdAsm_P16: return ARM::VLD1LNd16;
- case ARM::VLD1LNdAsm_I16: return ARM::VLD1LNd16;
- case ARM::VLD1LNdAsm_S16: return ARM::VLD1LNd16;
- case ARM::VLD1LNdAsm_U16: return ARM::VLD1LNd16;
+ case ARM::VLD1LNdAsm_16: return ARM::VLD1LNd16;
+ case ARM::VLD1LNdAsm_P16: return ARM::VLD1LNd16;
+ case ARM::VLD1LNdAsm_I16: return ARM::VLD1LNd16;
+ case ARM::VLD1LNdAsm_S16: return ARM::VLD1LNd16;
+ case ARM::VLD1LNdAsm_U16: return ARM::VLD1LNd16;
case ARM::VLD1LNdAsm_32: return ARM::VLD1LNd32;
case ARM::VLD1LNdAsm_F: return ARM::VLD1LNd32;
case ARM::VLD1LNdAsm_F32: return ARM::VLD1LNd32;
@@ -4778,6 +4810,70 @@
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
switch (Inst.getOpcode()) {
// Handle NEON VLD1 complex aliases.
+ case ARM::VLD1LNdWB_register_Asm_8:
+ case ARM::VLD1LNdWB_register_Asm_P8:
+ case ARM::VLD1LNdWB_register_Asm_I8:
+ case ARM::VLD1LNdWB_register_Asm_S8:
+ case ARM::VLD1LNdWB_register_Asm_U8:
+ case ARM::VLD1LNdWB_register_Asm_16:
+ case ARM::VLD1LNdWB_register_Asm_P16:
+ case ARM::VLD1LNdWB_register_Asm_I16:
+ case ARM::VLD1LNdWB_register_Asm_S16:
+ case ARM::VLD1LNdWB_register_Asm_U16:
+ case ARM::VLD1LNdWB_register_Asm_32:
+ case ARM::VLD1LNdWB_register_Asm_F:
+ case ARM::VLD1LNdWB_register_Asm_F32:
+ case ARM::VLD1LNdWB_register_Asm_I32:
+ case ARM::VLD1LNdWB_register_Asm_S32:
+ case ARM::VLD1LNdWB_register_Asm_U32: {
+ MCInst TmpInst;
+ // Shuffle the operands around so the lane index operand is in the
+ // right place.
+ TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
+ TmpInst.addOperand(Inst.getOperand(0)); // Vd
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn
+ TmpInst.addOperand(Inst.getOperand(3)); // alignment
+ TmpInst.addOperand(Inst.getOperand(4)); // Rm
+ TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
+ TmpInst.addOperand(Inst.getOperand(1)); // lane
+ TmpInst.addOperand(Inst.getOperand(5)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(6));
+ Inst = TmpInst;
+ return true;
+ }
+ case ARM::VLD1LNdWB_fixed_Asm_8:
+ case ARM::VLD1LNdWB_fixed_Asm_P8:
+ case ARM::VLD1LNdWB_fixed_Asm_I8:
+ case ARM::VLD1LNdWB_fixed_Asm_S8:
+ case ARM::VLD1LNdWB_fixed_Asm_U8:
+ case ARM::VLD1LNdWB_fixed_Asm_16:
+ case ARM::VLD1LNdWB_fixed_Asm_P16:
+ case ARM::VLD1LNdWB_fixed_Asm_I16:
+ case ARM::VLD1LNdWB_fixed_Asm_S16:
+ case ARM::VLD1LNdWB_fixed_Asm_U16:
+ case ARM::VLD1LNdWB_fixed_Asm_32:
+ case ARM::VLD1LNdWB_fixed_Asm_F:
+ case ARM::VLD1LNdWB_fixed_Asm_F32:
+ case ARM::VLD1LNdWB_fixed_Asm_I32:
+ case ARM::VLD1LNdWB_fixed_Asm_S32:
+ case ARM::VLD1LNdWB_fixed_Asm_U32: {
+ MCInst TmpInst;
+ // Shuffle the operands around so the lane index operand is in the
+ // right place.
+ TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
+ TmpInst.addOperand(Inst.getOperand(0)); // Vd
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
+ TmpInst.addOperand(Inst.getOperand(2)); // Rn
+ TmpInst.addOperand(Inst.getOperand(3)); // alignment
+ TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
+ TmpInst.addOperand(Inst.getOperand(1)); // lane
+ TmpInst.addOperand(Inst.getOperand(4)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(5));
+ Inst = TmpInst;
+ return true;
+ }
case ARM::VLD1LNdAsm_8:
case ARM::VLD1LNdAsm_P8:
case ARM::VLD1LNdAsm_I8:
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