[llvm-commits] [llvm] r144989 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h X86InstrFragmentsSIMD.td X86InstrSSE.td

[Duncan Sands]

Hi Craig,

> Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.

testcase?

Ciao, Duncan.

>
> Modified:
>      llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>      llvm/trunk/lib/Target/X86/X86ISelLowering.h
>      llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
>      llvm/trunk/lib/Target/X86/X86InstrSSE.td
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144989&r1=144988&r2=144989&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 03:02:40 2011
> @@ -14670,7 +14670,24 @@
>                        DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
>   }
>
> -static SDValue PerformSubCombine(SDNode *N, SelectionDAG&DAG) {
> +/// PerformADDCombine - Do target-specific dag combines on integer adds.
> +static SDValue PerformAddCombine(SDNode *N, SelectionDAG&DAG,
> +                                 const X86Subtarget *Subtarget) {
> +  EVT VT = N->getValueType(0);
> +  SDValue Op0 = N->getOperand(0);
> +  SDValue Op1 = N->getOperand(1);
> +
> +  // Try to synthesize horizontal adds from adds of shuffles.
> +  if ((Subtarget->hasSSSE3() || Subtarget->hasAVX())&&
> +      (VT == MVT::v8i16 || VT == MVT::v4i32)&&
> +      isHorizontalBinOp(Op0, Op1, true))
> +    return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
> +
> +  return OptimizeConditionalInDecrement(N, DAG);
> +}
> +
> +static SDValue PerformSubCombine(SDNode *N, SelectionDAG&DAG,
> +                                 const X86Subtarget *Subtarget) {
>     SDValue Op0 = N->getOperand(0);
>     SDValue Op1 = N->getOperand(1);
>
> @@ -14692,6 +14709,13 @@
>       }
>     }
>
> +  // Try to synthesize horizontal adds from adds of shuffles.
> +  EVT VT = N->getValueType(0);
> +  if ((Subtarget->hasSSSE3() || Subtarget->hasAVX())&&
> +      (VT == MVT::v8i16 || VT == MVT::v4i32)&&
> +      isHorizontalBinOp(Op0, Op1, false))
> +    return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
> +
>     return OptimizeConditionalInDecrement(N, DAG);
>   }
>
> @@ -14705,8 +14729,8 @@
>     case ISD::VSELECT:
>     case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
>     case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
> -  case ISD::ADD:            return OptimizeConditionalInDecrement(N, DAG);
> -  case ISD::SUB:            return PerformSubCombine(N, DAG);
> +  case ISD::ADD:            return PerformAddCombine(N, DAG, Subtarget);
> +  case ISD::SUB:            return PerformSubCombine(N, DAG, Subtarget);
>     case X86ISD::ADC:         return PerformADCCombine(N, DAG, DCI);
>     case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
>     case ISD::SHL:
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=144989&r1=144988&r2=144989&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sat Nov 19 03:02:40 2011
> @@ -178,6 +178,12 @@
>         /// BLEND family of opcodes
>         BLENDV,
>
> +      /// HADD - Integer horizontal add.
> +      HADD,
> +
> +      /// HSUB - Integer horizontal sub.
> +      HSUB,
> +
>         /// FHADD - Floating point horizontal add.
>         FHADD,
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=144989&r1=144988&r2=144989&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Sat Nov 19 03:02:40 2011
> @@ -41,6 +41,8 @@
>   def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
>   def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
>   def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
> +def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
> +def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
>   def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
>   def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
>   def X86cmpss   : SDNode<"X86ISD::FSETCCss",    SDTX86Cmpss>;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144989&r1=144988&r2=144989&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 03:02:40 2011
> @@ -5369,6 +5369,15 @@
>               (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
>     def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
>               (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
> +
> +  def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
> +            (PHADDWrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
> +            (PHADDDrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
> +            (PHSUBWrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
> +            (PHSUBDrr128 VR128:$src1, VR128:$src2)>;
>   }
>
>   let Predicates = [HasAVX] in {
> @@ -5383,6 +5392,15 @@
>               (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
>     def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
>               (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
> +
> +  def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
> +            (VPHADDWrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
> +            (VPHADDDrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
> +            (VPHSUBWrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
> +            (VPHSUBDrr128 VR128:$src1, VR128:$src2)>;
>   }
>
>   let Predicates = [HasAVX2] in {
> @@ -5392,6 +5410,15 @@
>               (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
>     def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
>               (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
> +
> +  def : Pat<(v16i16 (X86hadd VR256:$src1, VR256:$src2)),
> +            (VPHADDWrr256 VR256:$src1, VR256:$src2)>;
> +  def : Pat<(v8i32 (X86hadd VR256:$src1, VR256:$src2)),
> +            (VPHADDDrr256 VR256:$src1, VR256:$src2)>;
> +  def : Pat<(v16i16 (X86hsub VR256:$src1, VR256:$src2)),
> +            (VPHSUBWrr256 VR256:$src1, VR256:$src2)>;
> +  def : Pat<(v8i32 (X86hsub VR256:$src1, VR256:$src2)),
> +            (VPHSUBDrr256 VR256:$src1, VR256:$src2)>;
>   }
>
>   //===---------------------------------------------------------------------===//
>
>
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