[llvm-commits] [llvm] r144361 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll

[Eli Friedman]

Author: efriedma
Date: Thu Nov 10 21:16:38 2011
New Revision: 144361

URL: http://llvm.org/viewvc/llvm-project?rev=144361&view=rev
Log:
Make sure to expand SIGN_EXTEND_INREG for NEON vectors.  PR11319, round 3.


Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=144361&r1=144360&r2=144361&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Nov 10 21:16:38 2011
@@ -127,6 +127,7 @@
   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
   setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
   setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, VT.getSimpleVT(), Expand);
   if (VT.isInteger()) {
     setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
     setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);

Modified: llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll?rev=144361&r1=144360&r2=144361&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll Thu Nov 10 21:16:38 2011
@@ -13,3 +13,12 @@
   store <2 x i8> %3, <2 x i8>* @i8_res
   ret void
 }
+
+define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
+; CHECK: test_neon_ld_st_volatile_with_ashr_2xi8:
+  %1 = load volatile <2 x i8>* @i8_src1
+  %2 = load volatile <2 x i8>* @i8_src2
+  %3 = ashr <2 x i8> %1, %2
+  store volatile <2 x i8> %3, <2 x i8>* @i8_res
+  ret void
+}