[llvm-commits] [llvm] r144331 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb2-instructions.s
Jim Grosbach
grosbach at apple.com
Thu Nov 10 15:17:11 PST 2011
Author: grosbach
Date: Thu Nov 10 17:17:11 2011
New Revision: 144331
URL: http://llvm.org/viewvc/llvm-project?rev=144331&view=rev
Log:
Thumb2 parsing for push/pop w/ hi registers in the reglist.
rdar://10130228.
Modified:
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144331&r1=144330&r2=144331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Nov 10 17:17:11 2011
@@ -4526,16 +4526,21 @@
"in register list");
break;
}
+ // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
+ // so only issue a diagnostic for thumb1. The instructions will be
+ // switched to the t2 encodings in processInstruction() if necessary.
case ARM::tPOP: {
bool listContainsBase;
- if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
+ if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
+ !isThumbTwo())
return Error(Operands[2]->getStartLoc(),
"registers must be in range r0-r7 or pc");
break;
}
case ARM::tPUSH: {
bool listContainsBase;
- if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
+ if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
+ !isThumbTwo())
return Error(Operands[2]->getStartLoc(),
"registers must be in range r0-r7 or lr");
break;
@@ -4691,6 +4696,31 @@
}
break;
}
+ case ARM::tPOP: {
+ bool listContainsBase;
+ // If the register list contains any high registers, we need to use
+ // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
+ // should have generated an error in validateInstruction().
+ if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
+ return;
+ assert (isThumbTwo());
+ Inst.setOpcode(ARM::t2LDMIA_UPD);
+ // Add the base register and writeback operands.
+ Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
+ break;
+ }
+ case ARM::tPUSH: {
+ bool listContainsBase;
+ if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
+ return;
+ assert (isThumbTwo());
+ Inst.setOpcode(ARM::t2STMDB_UPD);
+ // Add the base register and writeback operands.
+ Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
+ break;
+ }
case ARM::t2MOVi: {
// If we can use the 16-bit encoding and the user didn't explicitly
// request the 32-bit variant, transform it here.
Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=144331&r1=144330&r2=144331&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Thu Nov 10 17:17:11 2011
@@ -1436,6 +1436,21 @@
@ CHECK: pli [sp, r2, lsl #1] @ encoding: [0x1d,0xf9,0x12,0xf0]
@ CHECK: pli [sp, r2] @ encoding: [0x1d,0xf9,0x02,0xf0]
+ at ------------------------------------------------------------------------------
+@ POP (alias)
+ at ------------------------------------------------------------------------------
+ pop {r2, r9}
+
+@ CHECK: pop.w {r2, r9} @ encoding: [0xbd,0xe8,0x04,0x02]
+
+
+ at ------------------------------------------------------------------------------
+@ PUSH (alias)
+ at ------------------------------------------------------------------------------
+ push {r2, r9}
+
+@ CHECK: push.w {r2, r9} @ encoding: [0x2d,0xe9,0x04,0x02]
+
@------------------------------------------------------------------------------
@ QADD/QADD16/QADD8
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