[llvm-commits] [llvm] r144213 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

[Chad Rosier]

Author: mcrosier
Date: Wed Nov  9 15:30:12 2011
New Revision: 144213

URL: http://llvm.org/viewvc/llvm-project?rev=144213&view=rev
Log:
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
rdar://10418009

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144213&r1=144212&r2=144213&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Nov  9 15:30:12 2011
@@ -846,9 +846,17 @@
   switch (VT.getSimpleVT().SimpleTy) {
     default:
       assert(false && "Unhandled load/store type!");
+    case MVT::i16:
+      if (isThumb2)
+        // Integer loads/stores handle 12-bit offsets.
+        needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
+      else
+        // ARM i16 integer loads/stores handle +/-imm8 offsets.
+        if (Addr.Offset > 255 || Addr.Offset < -255)
+          needsLowering = true;
+      break;
     case MVT::i1:
     case MVT::i8:
-    case MVT::i16:
     case MVT::i32:
       // Integer loads/stores handle 12-bit offsets.
       needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
@@ -932,14 +940,14 @@
   switch (VT.getSimpleVT().SimpleTy) {
     // This is mostly going to be Neon/vector support.
     default: return false;
-    case MVT::i16:
-      Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
-      RC = ARM::GPRRegisterClass;
-      break;
     case MVT::i8:
       Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12;
       RC = ARM::GPRRegisterClass;
       break;
+    case MVT::i16:
+      Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
+      RC = ARM::GPRRegisterClass;
+      break;
     case MVT::i32:
       Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
       RC = ARM::GPRRegisterClass;