[llvm-commits] [llvm] r143821 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-call.ll
Chad Rosier
mcrosier at apple.com
Sat Nov 5 13:16:15 PDT 2011
Author: mcrosier
Date: Sat Nov 5 15:16:15 2011
New Revision: 143821
URL: http://llvm.org/viewvc/llvm-project?rev=143821&view=rev
Log:
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
Added:
llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=143821&r1=143820&r2=143821&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Sat Nov 5 15:16:15 2011
@@ -557,7 +557,7 @@
unsigned ImmReg = createResultReg(TLI.getRegClassFor(SrcVT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ImmReg)
- .addImm(CI->getSExtValue()));
+ .addImm(CI->getZExtValue()));
return ImmReg;
}
@@ -1599,33 +1599,21 @@
switch (VA.getLocInfo()) {
case CCValAssign::Full: break;
case CCValAssign::SExt: {
- bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
- Arg, ArgVT, Arg);
- assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
- Emitted = true;
- ArgVT = VA.getLocVT();
+ EVT DestVT = VA.getLocVT();
+ unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT,
+ /*isZExt*/false);
+ assert (ResultReg != 0 && "Failed to emit a sext");
+ Arg = ResultReg;
break;
}
+ case CCValAssign::AExt:
+ // Intentional fall-through. Handle AExt and ZExt.
case CCValAssign::ZExt: {
- bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
- Arg, ArgVT, Arg);
- assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
- Emitted = true;
- ArgVT = VA.getLocVT();
- break;
- }
- case CCValAssign::AExt: {
- bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
- Arg, ArgVT, Arg);
- if (!Emitted)
- Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
- Arg, ArgVT, Arg);
- if (!Emitted)
- Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
- Arg, ArgVT, Arg);
-
- assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
- ArgVT = VA.getLocVT();
+ EVT DestVT = VA.getLocVT();
+ unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT,
+ /*isZExt*/true);
+ assert (ResultReg != 0 && "Failed to emit a sext");
+ Arg = ResultReg;
break;
}
case CCValAssign::BCvt: {
@@ -1643,7 +1631,7 @@
if (VA.isRegLoc() && !VA.needsCustom()) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
VA.getLocReg())
- .addReg(Arg);
+ .addReg(Arg);
RegArgs.push_back(VA.getLocReg());
} else if (VA.needsCustom()) {
// TODO: We need custom lowering for vector (v2f64) args.
@@ -1962,8 +1950,8 @@
Type *ArgTy = (*i)->getType();
MVT ArgVT;
- // FIXME: Should be able to handle i1, i8, and/or i16 parameters.
- if (!isTypeLegal(ArgTy, ArgVT))
+ if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
+ ArgVT != MVT::i1)
return false;
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
Flags.setOrigAlign(OriginalAlignment);
Added: llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll?rev=143821&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll Sat Nov 5 15:16:15 2011
@@ -0,0 +1,67 @@
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
+
+define i32 @t0(i1 zeroext %a) nounwind {
+ %1 = zext i1 %a to i32
+ ret i32 %1
+}
+
+define i32 @t1(i8 signext %a) nounwind {
+ %1 = sext i8 %a to i32
+ ret i32 %1
+}
+
+define i32 @t2(i8 zeroext %a) nounwind {
+ %1 = zext i8 %a to i32
+ ret i32 %1
+}
+
+define i32 @t3(i16 signext %a) nounwind {
+ %1 = sext i16 %a to i32
+ ret i32 %1
+}
+
+define i32 @t4(i16 zeroext %a) nounwind {
+ %1 = zext i16 %a to i32
+ ret i32 %1
+}
+
+define void @foo(i8 %a, i16 %b) nounwind {
+; ARM: foo
+; THUMB: foo
+;; Materialize i1 1
+; ARM: movw r2, #1
+;; zero-ext
+; ARM: and r2, r2, #1
+; THUMB: and r2, r2, #1
+ %1 = call i32 @t0(i1 zeroext 1)
+; ARM: sxtb r2, r1
+; ARM: mov r0, r2
+; THUMB: sxtb r2, r1
+; THUMB: mov r0, r2
+ %2 = call i32 @t1(i8 signext %a)
+; ARM: uxtb r2, r1
+; ARM: mov r0, r2
+; THUMB: uxtb r2, r1
+; THUMB: mov r0, r2
+ %3 = call i32 @t2(i8 zeroext %a)
+; ARM: sxth r2, r1
+; ARM: mov r0, r2
+; THUMB: sxth r2, r1
+; THUMB: mov r0, r2
+ %4 = call i32 @t3(i16 signext %b)
+; ARM: uxth r2, r1
+; ARM: mov r0, r2
+; THUMB: uxth r2, r1
+; THUMB: mov r0, r2
+ %5 = call i32 @t4(i16 zeroext %b)
+
+;; A few test to check materialization
+;; Note: i1 1 was materialized with t1 call
+; ARM: movw r1, #255
+%6 = call i32 @t2(i8 zeroext 255)
+; ARM: movw r1, #65535
+; THUMB: movw r1, #65535
+%7 = call i32 @t4(i16 zeroext 65535)
+ ret void
+}
More information about the llvm-commits
mailing list