[llvm-commits] [llvm] r143739 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Chad Rosier
mcrosier at apple.com
Fri Nov 4 15:29:00 PDT 2011
Author: mcrosier
Date: Fri Nov 4 17:29:00 2011
New Revision: 143739
URL: http://llvm.org/viewvc/llvm-project?rev=143739&view=rev
Log:
Enable support for materializing i1, i8, and i16 integers via move immediate.
Modified:
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=143739&r1=143738&r2=143739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Nov 4 17:29:00 2011
@@ -545,22 +545,27 @@
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
- // For now 32-bit only.
- if (VT != MVT::i32) return false;
-
- unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
+ if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
+ return false;
// If we can do this in a single instruction without a constant pool entry
// do so now.
const ConstantInt *CI = cast<ConstantInt>(C);
if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
+ unsigned ImmReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
- TII.get(Opc), DestReg)
+ TII.get(Opc), ImmReg)
.addImm(CI->getSExtValue()));
- return DestReg;
+ return ImmReg;
}
+ // For now 32-bit only.
+ if (VT != MVT::i32)
+ return false;
+
+ unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
+
// MachineConstantPool wants an explicit alignment.
unsigned Align = TD.getPrefTypeAlignment(C->getType());
if (Align == 0) {
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