[llvm-commits] [llvm] r143108 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Jim Grosbach
grosbach at apple.com
Thu Oct 27 10:16:55 PDT 2011
Author: grosbach
Date: Thu Oct 27 12:16:55 2011
New Revision: 143108
URL: http://llvm.org/viewvc/llvm-project?rev=143108&view=rev
Log:
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
rdar://10348584
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=143108&r1=143107&r2=143108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Oct 27 12:16:55 2011
@@ -3921,7 +3921,9 @@
def : t2InstAlias<"ldrsh${p} $Rt, $addr",
(t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
-// Alias for MVN without the ".w" optional width specifier.
+// Alias for MVN with(out) the ".w" optional width specifier.
+def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
+ (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
(t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=143108&r1=143107&r2=143108&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Thu Oct 27 12:16:55 2011
@@ -1231,7 +1231,7 @@
mvns r0, #0x3fc0000
itte eq
mvnseq r1, #12
- mvneq r1, #12
+ mvneq.w r1, #12
mvnne r1, #12
@ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08]
@@ -1250,7 +1250,7 @@
mvns r2, r3
mvn r5, r6, lsl #19
mvn r5, r6, lsr #9
- mvn r5, r6, asr #4
+ mvn.w r5, r6, asr #4
mvn r5, r6, ror #6
mvn r5, r6, rrx
it eq
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