[llvm-commits] [llvm] r143072 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Chad Rosier
mcrosier at apple.com
Wed Oct 26 15:47:55 PDT 2011
Author: mcrosier
Date: Wed Oct 26 17:47:55 2011
New Revision: 143072
URL: http://llvm.org/viewvc/llvm-project?rev=143072&view=rev
Log:
Factor out an EmitCmp function that can be used by both SelectCmp and
SelectBranch. No functional change intended.
Modified:
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=143072&r1=143071&r2=143072&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Oct 26 17:47:55 2011
@@ -173,6 +173,7 @@
private:
bool isTypeLegal(Type *Ty, MVT &VT);
bool isLoadTypeLegal(Type *Ty, MVT &VT);
+ bool ARMEmitCmp(Type *Ty, const Value *Src1Value, const Value *Src2Value);
bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
bool ARMComputeAddress(const Value *Obj, Address &Addr);
@@ -1214,54 +1215,58 @@
return true;
}
-bool ARMFastISel::SelectCmp(const Instruction *I) {
- const CmpInst *CI = cast<CmpInst>(I);
-
+bool ARMFastISel::ARMEmitCmp(Type *Ty, const Value *Src1Value,
+ const Value *Src2Value) {
MVT VT;
- Type *Ty = CI->getOperand(0)->getType();
if (!isTypeLegal(Ty, VT))
return false;
- bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
- if (isFloat && !Subtarget->hasVFP2())
+ if ((Ty->isFloatTy() || Ty->isDoubleTy()) && !Subtarget->hasVFP2())
return false;
unsigned CmpOpc;
- unsigned CondReg;
switch (VT.SimpleTy) {
default: return false;
// TODO: Verify compares.
case MVT::f32:
CmpOpc = ARM::VCMPES;
- CondReg = ARM::FPSCR;
break;
case MVT::f64:
CmpOpc = ARM::VCMPED;
- CondReg = ARM::FPSCR;
break;
case MVT::i32:
CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
- CondReg = ARM::CPSR;
break;
}
+ unsigned Src1 = getRegForValue(Src1Value);
+ if (Src1 == 0) return false;
+
+ unsigned Src2 = getRegForValue(Src2Value);
+ if (Src2 == 0) return false;
+
+ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
+ .addReg(Src1).addReg(Src2));
+ return true;
+}
+
+bool ARMFastISel::SelectCmp(const Instruction *I) {
+ const CmpInst *CI = cast<CmpInst>(I);
+
// Get the compare predicate.
ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
// We may not handle every CC for now.
if (ARMPred == ARMCC::AL) return false;
- unsigned Arg1 = getRegForValue(CI->getOperand(0));
- if (Arg1 == 0) return false;
-
- unsigned Arg2 = getRegForValue(CI->getOperand(1));
- if (Arg2 == 0) return false;
-
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
- .addReg(Arg1).addReg(Arg2));
+ // Emit the compare.
+ Type *Ty = CI->getOperand(0)->getType();
+ if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
+ return false;
// For floating point we need to move the result to a comparison register
// that we can then use for branches.
+ bool isFloat = Ty->isFloatTy() || Ty->isDoubleTy();
if (isFloat)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::FMSTAT)));
@@ -1275,6 +1280,7 @@
Constant *Zero
= ConstantInt::get(Type::getInt32Ty(*Context), 0);
unsigned ZeroReg = TargetMaterializeConstant(Zero);
+ unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
.addReg(ZeroReg).addImm(1)
.addImm(ARMPred).addReg(CondReg);
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