[llvm-commits] [llvm] r142896 - in /llvm/trunk/test/Bitcode: sse42_crc32.ll sse42_crc32.ll.bc ssse3_palignr.ll ssse3_palignr.ll.bc

[Chad Rosier]

Author: mcrosier
Date: Mon Oct 24 20:22:20 2011
New Revision: 142896

URL: http://llvm.org/viewvc/llvm-project?rev=142896&view=rev
Log:
Fix these test cases to not use .bc files.  Otherwise, we run into issues with
bitcode reader/writer backward compatibility.

Removed:
    llvm/trunk/test/Bitcode/sse42_crc32.ll.bc
    llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc
Modified:
    llvm/trunk/test/Bitcode/sse42_crc32.ll
    llvm/trunk/test/Bitcode/ssse3_palignr.ll

Modified: llvm/trunk/test/Bitcode/sse42_crc32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll?rev=142896&r1=142895&r2=142896&view=diff
==============================================================================
--- llvm/trunk/test/Bitcode/sse42_crc32.ll (original)
+++ llvm/trunk/test/Bitcode/sse42_crc32.ll Mon Oct 24 20:22:20 2011
@@ -3,7 +3,7 @@
 ;
 ; Rdar: 9472944
 ;
-; RUN: llvm-dis < %s.bc | FileCheck %s
+; RUN: opt < %s | llvm-dis | FileCheck %s
 
 ; crc32.8 should upgrade to crc32.32.8
 ; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
@@ -26,3 +26,18 @@
 ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64(
 
 
+define void @foo() nounwind readnone ssp {
+entry:
+  %0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0)
+  %1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0)
+  %2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0)
+  %3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0)
+  %4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0)
+  ret void
+}
+
+declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone
+declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone
+declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone
+declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone
+declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone

Removed: llvm/trunk/test/Bitcode/sse42_crc32.ll.bc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll.bc?rev=142895&view=auto
==============================================================================
Binary file - no diff available.

Modified: llvm/trunk/test/Bitcode/ssse3_palignr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll?rev=142896&r1=142895&r2=142896&view=diff
==============================================================================
--- llvm/trunk/test/Bitcode/ssse3_palignr.ll (original)
+++ llvm/trunk/test/Bitcode/ssse3_palignr.ll Mon Oct 24 20:22:20 2011
@@ -1,2 +1,82 @@
-; RUN: llvm-dis < %s.bc | FileCheck %s 
+; RUN: opt < %s | llvm-dis | FileCheck %s
 ; CHECK-NOT: {@llvm\\.palign}
+
+define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i64>> [#uses=1]
+  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+  ret <4 x i32> %3
+}
+
+define double @align8(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> [#uses=1]
+  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
+  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
+  ret double %retval12
+}
+
+declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
+
+define double @align7(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>> [#uses=1]
+  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
+  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
+  ret double %retval12
+}
+
+define double @align6(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> [#uses=1]
+  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
+  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
+  ret double %retval12
+}
+
+define double @align5(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> [#uses=1]
+  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
+  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
+  ret double %retval12
+}
+
+define <4 x i32> @align4(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i64>> [#uses=1]
+  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+  ret <4 x i32> %3
+}
+
+declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <4 x i32> @align3(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i64>> [#uses=1]
+  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @align2(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i64>> [#uses=1]
+  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+  ret <4 x i32> %3
+}

Removed: llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc?rev=142895&view=auto
==============================================================================
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