[llvm-commits] [llvm] r142817 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/neont2.txt

[Owen Anderson]

Author: resistor
Date: Mon Oct 24 13:04:29 2011
New Revision: 142817

URL: http://llvm.org/viewvc/llvm-project?rev=142817&view=rev
Log:
Fix a NEON disassembly case that was broken in the recent refactorings.  As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/neont2.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=142817&r1=142816&r2=142817&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Oct 24 13:04:29 2011
@@ -1974,12 +1974,6 @@
       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
         return MCDisassembler::Fail;
       break;
-    case ARM::VLD2b8:
-    case ARM::VLD2b16:
-    case ARM::VLD2b32:
-    case ARM::VLD2b8_UPD:
-    case ARM::VLD2b16_UPD:
-    case ARM::VLD2b32_UPD:
     case ARM::VLD3q8:
     case ARM::VLD3q16:
     case ARM::VLD3q32:

Modified: llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt?rev=142817&r1=142816&r2=142817&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neont2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Mon Oct 24 13:04:29 2011
@@ -1584,3 +1584,7 @@
 # CHECK: vst4.16	{d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
 0xc0 0xf9 0x4f 0x1b
 # CHECK: vst4.32	{d17[0], d19[0], d21[0], d23[0]}, [r0]
+
+0x63 0xf9 0x37 0xc9
+# CHECK: vld2.8	{d28, d29}, [r3, :256], r7
+